參數(shù)資料
型號(hào)： IspLSI2032E-225LT44
廠(chǎng)商： Lattice Semiconductor Corporation
英文描述： In-System Programmable SuperFAST High Density PLD
中文描述： 在系統(tǒng)可編程超快高密度可編程邏輯器件
文件頁(yè)數(shù)： 11/14頁(yè)
文件大?。?/td> 173K
代理商： ISPLSI2032E-225LT44
Specifications
ispLSI 2032E
11
Pin Description
1. Pins have dual function capability.
2. NC pins are not to be connected to any active signals, V
CC
or GND.
Input/Output Pins
—
These are the general purpose
I/O pins used by the logic array.
NAME
Table 2-0002/2032E
44-PIN PLCC
PIN NUMBERS
DESCRIPTION
15,
19,
25,
29,
37,
41,
3,
7,
16,
20,
26,
30,
38,
42,
4,
8,
17,
21,
27,
31,
39,
43,
5,
9,
I/O 0 - I/O 3
I/O 4 - I/O 7
I/O 8 - I/O 11
I/O 12 - I/O 15
I/O 16 - I/O 19
I/O 20 - I/O 23
I/O 24 - I/O 27
I/O 28 - I/O 31
18,
22,
28,
32,
40,
44,
6,
10
Global Output Enable input pin.
2
GOE 0
1,
23
GND
V
CC
Supply voltage for output drivers, 5V or 3.3V. All
VCCIO pins must be connected to the same voltage
level.
12, 34
17, 39
6,
28
24, 48
6,
30
VCC
12, 18, 36, 42
VCCIO
Ground (GND)
Input
—
This pin performs two functions. When
BSCAN
is logic low, it functions as an input pin to load
programming data into the device. TDI/IN0 also is used
as one of the two control pins for the ISP state
machine. When
BSCAN
is high, it functions as a
dedicated input pin.
Dedicated Clock input. This clock input is connected to
one of the clock inputs of all the GLBs on the device.
This pin performs two functions:
- Dedicated clock input. This clock input is brought
into the Clock Distribution Network, and can optionally
be routed to any GLB and/or I/O cell on the device.
- Active Low (0) Reset pin which resets all of the GLB
and I/O registers in the device.
Input
—
Dedicated in-system programming enable
input pin. This pin is brought low to enable the
programming mode. The TMS, TDI, TDO and TCK
controls become active.
RESET
/Y1
Y0
TDI/IN 0
1
BSCAN
TMS/NC
2
Input
—
When in ISP mode, controls operation of ISP
state machine.
Output/Input
—
This pin performs two functions. When
BSCAN
is logic low, it functions as an output pin to
read serial shift register data. When
BSCAN
is high, it
functions as a dedicated input pin.
TDO/IN 1
1
Input
—
This pin performs two functions. When
BSCAN
is logic low, it functions as a clock pin for the
Serial Shift Register. When
BSCAN
is high, it
functions as a dedicated clock input. This clock input
is brought into the Clock Distribution Network and
can be routed to any GLB and/or I/O cell on the
device.
TCK/Y2
1
35
11
14
13
36
24
33
44-PIN TQFP
PIN NUMBERS
48-PIN TQFP
PIN NUMBERS
9,
13,
19,
23,
31
35,
41,
1,
10,
14,
20,
24,
32,
36,
42,
2,
11,
15,
21,
25,
33,
37,
43,
3,
12,
16,
22,
26,
34,
38,
44,
4
40
5
29
7
8
30
18
27
9,
14,
20,
25,
33,
38,
44,
1,
10,
15,
21,
26,
34,
39,
45,
2,
11,
16,
22,
27,
35,
40,
46,
3,
13,
17,
23,
28,
37,
41,
47,
4
43
5
31
7
8
32
19
29
相關(guān)PDF資料
PDF描述
IspLSI2032E-225LT48 In-System Programmable SuperFAST High Density PLD
ISPLSI2032E-135LT48 In-System Programmable SuperFAST⑩ High Density PLD
IspLSI2032E-135LT48 In-System Programmable SuperFAST High Density PLD
ISPLSI2032E-180LT48 In-System Programmable SuperFAST⑩ High Density PLD
IspLSI2032E-180LT48 In-System Programmable SuperFAST High Density PLD
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ISPLSI2032E-225LT48 功能描述:CPLD - 復(fù)雜可編程邏輯器件 RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類(lèi)型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
ISPLSI2032LV60LJ 制造商:LATTICE 功能描述:New
ISPLSI2032LV-60LJ 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:Electrically-Erasable Complex PLD
ISPLSI2032LV-60LJI 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:Electrically-Erasable Complex PLD
ISPLSI2032LV-60LT44 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:Electrically-Erasable Complex PLD
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