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參數(shù)資料
| 型號： | ISPLSI1024EA-200LT100 |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | PLD |
| 英文描述： | In-System Programmable High Density PLD |
| 中文描述： | EE PLD, 6 ns, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁數(shù)： | 7/13頁 |
| 文件大?。?/td> | 162K |
| 代理商： | ISPLSI1024EA-200LT100 |
7
Specifications
ispLSI 1024EA
Internal Timing Parameters
1
GRP Delay, 24 GLB Loads
t
iobp
t
iolat
t
iosu
t
ioh
t
ioco
t
ior
t
din
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
Table 2-0036A/1024EA
v.2.5
Inputs
UNITS
DESCRIPTION
#
2
PARAM.
22 I/O Register Bypass
23 I/O Latch Delay
24 I/O Register Setup Time before Clock
25 I/O Register Hold Time after Clock
26 I/O Register Clock to Out Delay
27 I/O Register Reset to Out Delay
28 Dedicated Input Delay
ns
ns
ns
ns
ns
ns
ns
t
grp24
GLB
t
4ptbpc
t
4ptbpr
33
ns
t
1ptxor
t
20ptxor 37 20 Product Term/XOR Path Delay
t
xoradj
38 XOR Adjacent Path Delay
t
gbp
39 GLB Register Bypass Delay
t
gsu
40 GLB Register Setup Time before Clock
t
gh
41 GLB Register Hold Time after Clock
t
gco
42 GLB Register Clock to Output Delay
t
gro
43 GLB Register Reset to Output Delay
t
ptre
44 GLB Product Term Reset to Register Delay
t
ptoe
45 GLB Product Term Output Enable to I/O Cell Delay
t
ptck
46 GLB Product Term Clock Delay
t
gfb
47 GLB Feedback Delay
36 1 ProductTerm/XOR Path Delay
ns
ns
ns
ns
ns
ns
ns
3
ns
ns
ns
ns
ns
ORP
t
orp
t
orpbp
GRP
t
grp1
34 4 ProductTerm Bypass Path Delay (Combinatorial)
ns
35 4 Product Term Bypass Path Delay (Registered)
ns
48 ORP Delay
49 ORP Bypass Delay
ns
ns
t
grp16
32 GRP Delay, 16 GLB Loads
ns
t
grp8
31 GRP Delay, 8 GLB Loads
ns
t
grp4
30 GRP Delay, 4 GLB Loads
ns
29 GRP Delay, 1 GLB Load
ns
MIN. MAX.
-200
—
—
3.0
0.0
—
—
—
—
—
—
—
—
—
—
—
—
1.5
—
—
—
0.2
1.0
—
—
—
—
—
—
0.3
4.0
—
—
4.0
4.0
1.1
2.5
1.9
1.9
1.9
0.6
1.4
3.8
2.5
2.1
2.5
0.0
1.7
1.8
—
—
0.8
0.1
2.1
1.7
1.5
1.3
-100
MIN.
MIN.
MAX.
MAX.
-125
—
—
3.4
0.0
—
—
—
—
—
—
—
—
—
—
—
—
3.5
—
—
1.4
4.0
—
—
—
—
—
—
0.3
4.0
—
—
4.6
4.6
1.9
2.9
3.6
3.6
3.6
1.2
1.4
4.9
3.8
5.7
3.9
3.4
3.1
—
—
1.3
0.2
2.5
2.1
1.9
1.7
—
—
3.0
0.0
—
—
—
—
—
—
—
—
—
—
—
—
2.8
—
—
0.3
3.5
—
—
—
—
—
—
0.4
4.0
—
—
5.0
5.0
2.2
3.3
4.3
4.3
4.3
2.1
1.7
5.0
4.5
7.2
4.7
4.9
3.8
—
—
—
0.3
—
0.3
1.4
0.4
2.9
2.5
2.3
2.1
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| ISPLSI1032 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable High Density PLD |
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