參數(shù)資料
型號: ISPLSI1016-90LT
英文描述: Electrically-Erasable Complex PLD
中文描述: 電可擦除復雜可編程邏輯器件
文件頁數(shù): 7/12頁
文件大小: 120K
代理商: ISPLSI1016-90LT
Specifications
ispLSI 1048
7
USEispLS 1048EAFORNEW
COMMERCAL&INDUSTRAL
DESGNS
Internal Timing Parameters
1
ns
ns
ns
ns
ns
ns
ns
ns
ns
6.7
5.3
1.3
5.3
1.3
4.0
6.7
6.7
6.7
8.0
6.6
8.0
6.6
10.6
Outputs
t
ob
t
oen
t
odis
Clocks
t
gy0
t
gy1/2
t
gcp
t
ioy2/3
t
iocp
Global Reset
t
gr
47
49
50
51
52
53
54
55
Output Buffer Delay
I/O Cell OE to Output Disabled
Clock Delay, Y0 to Global GLB Clock Line (Ref. clock)
Clock Delay, Y1 or Y2 to Global GLB Clock Line
Clock Delay, Clock GLB to Global GLB Clock Line
Clock Delay, Y2 or Y3 to I/O Cell Global Clock Line
Clock Delay, Clock GLB to I/O Cell Global Clock Line
Global Reset to GLB and I/O Registers
MIN. MAX.
DESCRIPTION
PARAMETER
UNITS
-50
#
2
5.0
4.0
1.0
4.0
1.0
3.0
5.0
5.0
6.0
5.0
6.0
5.0
8.0
MIN. MAX.
-70
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
4.2
3.3
0.8
3.3
0.8
2.5
4.2
4.2
5.0
4.2
5.0
4.2
9.2
MIN. MAX.
-80
相關PDF資料
PDF描述
ISPLSI1016-90LT44 Electrically-Erasable Complex PLD
ISPLSI1016E100LJ Electrically-Erasable Complex PLD
ISPLSI1016E100LT44 Electrically-Erasable Complex PLD
ISPLSI1016E125LJ Electrically-Erasable Complex PLD
ISPLSI1016E125LT44 Electrically-Erasable Complex PLD
相關代理商/技術參數(shù)
參數(shù)描述
ispLSI1016-90LT44 功能描述:CPLD - 復雜可編程邏輯器件 USE ispMACH 4000V RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
ISPLSI1016E 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable High Density PLD
ISPLSI1016E_02 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable High Density PLD
ISPLSI1016E_06 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable High Density PLD
ISPLSI1016E100LJ 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable High Density PLD