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參數(shù)資料
| 型號： | ISPLSI 2064A-80LTN100I |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁數(shù)： | 14/14頁 |
| 文件大小： | 0K |
| 描述： | IC PLD ISP 64I/O 15NS 100TQFP |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 系列： | ispLSI® 2000A |
| 可編程類型： | 系統(tǒng)內(nèi)可編程 |
| 最大延遲時間 tpd(1)： | 15.0ns |
| 電壓電源 - 內(nèi)部： | 4.5 V ~ 5.5 V |
| 邏輯元件/邏輯塊數(shù)目： | 16 |
| 宏單元數(shù)： | 64 |
| 門數(shù)： | 2000 |
| 輸入/輸出數(shù)： | 64 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-LQFP |
| 供應(yīng)商設(shè)備封裝： | 100-TQFP（14x14） |
| 包裝： | 托盤 |
| 其它名稱： | ISPLSI2064A-80LTN100I |
9
Specifications ispLSI 2064/A
USE
ispLSI
2064E
FOR
NEW
DESIGNS
Pin Description
I/O 0 - I/O 3
I/O 4 - I/O 7
I/O 8 - I/O 11
I/O 12 - I/O 15
I/O 16 - I/O 19
I/O 20 - I/O 23
I/O 24 - I/O 27
I/O 28 - I/O 31
I/O 32 - I/O 35
I/O 36 - I/O 39
I/O 40 - I/O 43
I/O 44 - I/O 47
I/O 48 - I/O 51
I/O 52 - I/O 55
I/O 56 - I/O 59
I/O 60 - I/O 63
NAME
DESCRIPTION
1. NC pins are not to be connected to any active signals, VCC or GND.
2. Pins have dual function capability.
Table 2-0002A-08isp/2064
PLCC PIN NUMBERS
Input — Dedicated in-system programming enable pin. This pin is brought low to
enable the programming mode. When low, the MODE, SDI, SDO and SCLK
controls become active.
Input — This pin performs two functions. When
ispEN is logic low, it functions
as an input pin to load programming data into the device. SDI/IN 0 also is used
as one of the two control pins for the ISP state machine. When
ispEN is high, it
functions as a dedicated pin input.
Input — This pin performs two functions. When
ispEN is logic low, it functions
as a pin to control the operation of the ISP state machine. When
ispEN is high,
it functions as a dedicated input pin.
Output/Input — This pin performs two functions. When
ispEN is logic low, it
functions as an output pin to read serial shift register data. When
ispEN is high,
it functions as a dedicated input pin.
Input — This pin performs two functions. When
ispEN is logic low, it functions
as a clock pin for the Serial Shift Register. When
ispEN is high, it functions as
a dedicated input pin.
No Connect
NC1
VCC
21,
65
GND
1,
SDO/IN 22
44
MODE/ IN 12
42
SDI/ IN 02
25
ispEN
23
RESET
24
SCLK/IN 32
61
22,
43,
64
Y0, Y1, Y2
20,
66,
GOE 0, GOE 1
67,
84
63
Input/Output Pins — These are the general purpose I/O pins used by the logic
array.
Global Output Enable input pins.
Dedicated Clock input. This clock input is connected to one of the clock inputs of
all the GLBs in the device.
Active Low (0) Reset pin which resets all registers in the device.
Ground (GND)
Vcc
26,
27,
28,
29,
30,
31,
32,
33,
34,
35,
36,
37,
38,
39,
40,
41,
2,
19,
62
45,
46,
47,
48,
49,
50,
51,
52,
53,
54,
55,
56,
57,
58,
59,
60,
68,
69,
70,
71,
72,
73,
74,
75,
76,
77,
78,
79,
80,
81,
82,
83,
3,
4,
5,
6,
7,
8,
9,
10,
11,
12,
13,
14,
15,
16,
17,
18
Select
devices
have
been
discontinued.
See
Ordering
Information
section
for
product
status.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ispLSI2064A-80LTN100I | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 USE ispMACH 4000V RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ISPLSI2064E-100LT | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Electrically-Erasable Complex PLD |
| ISPLSI2064E-100LT100 | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ISPLSI2064E-135LT | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Electrically-Erasable Complex PLD |
| ISPLSI2064E-135LT100 | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
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