Specifications ispLSI 1048EA 11 USE ispMA CH 4A5 FOR NEW 5V DESIGNS Pin Description Dedicated Clock input. This clock input is brought into the" />
參數(shù)資料
型號: ISPLSI 1048EA-100LT128
廠商: Lattice Semiconductor Corporation
文件頁數(shù): 3/14頁
文件大小: 0K
描述: IC PLD ISP 96I/O 10NS 128TQFP
標準包裝: 90
系列: ispLSI® 1000EA
可編程類型: 系統(tǒng)內(nèi)可編程
最大延遲時間 tpd(1): 10.0ns
電壓電源 - 內(nèi)部: 4.75 V ~ 5.25 V
邏輯元件/邏輯塊數(shù)目: 48
門數(shù): 8000
輸入/輸出數(shù): 96
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 128-LQFP
供應(yīng)商設(shè)備封裝: 128-TQFP(14x14)
包裝: 托盤
其它名稱: ISPLSI1048EA-100LT128
Specifications ispLSI 1048EA
11
USE
ispMA
CH
4A5
FOR
NEW
5V
DESIGNS
Pin Description
Dedicated Clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any GLB on the
device.
Dedicated Clock input. This clock input is connected to one of the clock
inputs of all of the GLBs on the device.
Input/Output Pins - These are the general purpose I/O pins used by the
logic array.
NAME
Table 2-0002C/1048EA
PQFP / TQFP PIN NUMBERS
DESCRIPTION
21,
27,
34,
40,
52,
58,
66,
72,
85,
91,
98,
104,
117,
123,
2,
8,
22,
28,
35,
41,
53,
59,
67,
73,
86,
92,
99,
105,
118,
124,
3,
9,
23,
29,
36,
42,
54,
60,
68,
74,
87,
93,
100,
106,
119,
125,
4,
10,
I/O 0 - I/O 5
I/O 6 - I/O 11
I/O 12 - I/O 17
I/O 18 - I/O 23
I/O 24 - I/O 29
I/O 30 - I/O 35
I/O 36 - I/O 41
I/O 42 - I/O 47
I/O 48 - I/O 53
I/O 54 - I/O 59
I/O 60 - I/O 65
I/O 66 - I/O 71
I/O 72 - I/O 77
I/O 78 - I/O 83
I/O 84 - I/O 89
I/O 90 - I/O 95
24,
30,
37,
43,
55,
61,
69,
75,
88,
94,
101,
107,
120,
126,
5,
11,
25,
31,
38,
44,
56,
62,
70,
76,
89,
95,
102,
108,
121,
127,
6,
12,
83
Y1
15
Y0
46
TMS
Input - Controls the operation of the ISP JTAG state machine.
Ground (GND)
GND
V
VCC
CC
26,
32,
39,
45,
57,
63,
71,
77,
90,
96,
103,
109,
122,
128,
7,
13
Global Output Enable input pins.
GOE0, GOE1
Dedicated input pins to the device.
IN 2, IN 4, IN 6-IN 11
64,
114
47,
51
84,
110,
111,
115,
116,
14
Input - Functions as an input pin to load programming data into the
device and also is used as one of the two control pins for the ISP JTAG
state machine.
20
TDI
50
TDO
Output - Functions as an output pin to read serial shift register data.
78
TCK
Input - Functions as a clock pin for the Serial Shift Register.
Active Low (0) Reset pin which resets all of the GLB and I/O registers in
the device.
19
RESET
Dedicated Clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any GLB and/or
any I/O cell on the device.
80
Y2
Dedicated Clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any I/O cell on the
device.
79
Y3
1,
97,
17,
112
33,
49,
65,
81,
16,
48,
82,
113
Supply voltage for output drivers, 5V or 3.3V.
VCCIO
18
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ISPLSI1048EA-100LT128 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable High Density PLD
ISPLSI1048EA-125LQ128 功能描述:CPLD - 復(fù)雜可編程邏輯器件 RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
ISPLSI1048EA-125LT128 功能描述:CPLD - 復(fù)雜可編程邏輯器件 RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
ISPLSI1048EA-170LQ128 功能描述:CPLD - 復(fù)雜可編程邏輯器件 RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
ISPLSI1048EA-170LT128 功能描述:CPLD - 復(fù)雜可編程邏輯器件 RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100