Specifications ispLSI 1016E USE ispLSI 1016EA FOR NEW DESIGNS Input - This pin performs two functions. When ispEN is logic low, it functions" />
參數(shù)資料
型號(hào): ISPLSI 1016E-125LJN
廠商: Lattice Semiconductor Corporation
文件頁數(shù): 2/13頁
文件大?。?/td> 0K
描述: IC PLD ISP 32I/O 125MHZ 44PLCC
標(biāo)準(zhǔn)包裝: 26
系列: ispLSI® 1000E
可編程類型: 系統(tǒng)內(nèi)可編程
最大延遲時(shí)間 tpd(1): 7.5ns
電壓電源 - 內(nèi)部: 4.75 V ~ 5.25 V
邏輯元件/邏輯塊數(shù)目: 16
門數(shù): 2000
輸入/輸出數(shù): 32
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 44-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 44-PLCC(16.58x16.58)
包裝: 管件
其它名稱: ISPLSI1016E-125LJN
10
Specifications ispLSI 1016E
USE
ispLSI
1016EA
FOR
NEW
DESIGNS
Input - This pin performs two functions. When ispEN is logic low, it functions
as an input pin to load programming data into the device. It is a dedicated
input pin when ispEN is logic high.SDI/IN0 also is used as one of the two
control pins for the isp state machine.
Dedicated Clock input. This clock input is connected to one of the clock
inputs of all the GLBs on the device.
This pin performs two functions:
Input - Dedicated in-system programming enable input pin. This pin is
brought low to enable the programming mode. The MODE, SDI, SDO and
SCLK controls become active.
This is a dual function pin. It can be used either as Global Output Enable for
all I/O cells or it can be used as a dedicated input pin.
Input/Output Pins - These are the general purpose I/O pins used by the logic
array.
NAME
Table 2-0002C-16-isp
DESCRIPTION
I/O 0 - I/O 3
I/O 4 - I/O 7
I/O 8 - I/O 11
I/O 12 - I/O 15
I/O 16 - I/O 19
I/O 20 - I/O 23
I/O 24 - I/O 27
I/O 28 - I/O 31
GOE 0/IN 32
Y1/RESET
Y0
SDI/IN 01
ispEN
MODE/IN 21
Input - This pin performs two functions. When ispEN is logic low, it functions
as a pin to control the operation of the isp state machine. It is a dedicated
input pin when ispEN is logic high.
GND
Vcc
VCC
- Dedicated clock input. This clock input is brought into the Clock
Distribution Network, and can optionally be routed to any GLB and/or
I/O cell on the device.
Output/Input - This pin performs two functions. When ispEN is logic low, it
functions as an output pin to read serial shift register data. It is a dedicated
input pin when ispEN is logic high.
SDO/IN 11
Input - This pin performs two functions. When ispEN is logic low, it
functions as a clock pin for the Serial Shift Register. It is a dedicated clock
input when ispEN is logic high. This clock input is brought into the Clock
Distribution Network, and can optionally be routed to any GLB and/or I/O
cell on the device.
SCLK/Y21
Ground (GND)
- Active Low (0) Reset pin which resets all of the GLB and I/O registers
in the device.
PLCC
PIN NUMBERS
15,
19,
25,
29,
37,
41,
3,
7,
16,
20,
26,
30,
38,
42,
4,
8,
17,
21,
27,
31,
39,
43,
5,
9,
18,
22,
28,
32,
40,
44,
6,
10
2
35
11
14
13
36
1,
12,
24
33
23
34
1. Pins have dual function capability.
2. Pins have dual function capability which is software selectable.
TQFP
PIN NUMBERS
9,
13,
19,
23,
31,
35,
41,
1,
10,
14,
20,
24,
32,
36,
42,
2,
11,
15,
21,
25,
33,
37,
43,
3,
12,
16,
22,
26,
34,
38,
44,
4
40
29
5
8
7
30
17,
6,
18
27
39
28
Pin Description
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ispLSI1016E-125LJN 功能描述:CPLD - 復(fù)雜可編程邏輯器件 USE ispMACH 4000V RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
ISPLSI1016E125LJNI 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable High Density PLD
ISPLSI1016E125LT44 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable High Density PLD
ispLSI1016E-125LT44 功能描述:CPLD - 復(fù)雜可編程邏輯器件 USE ispMACH 4000V RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
ISPLSI1016E125LT44I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable High Density PLD