ispLSI 1016 In-System Programmable High Density PLD 1 Functional Block Diagr" />
參數(shù)資料
型號: ISPLSI 1016-60LJI
廠商: Lattice Semiconductor Corporation
文件頁數(shù): 10/17頁
文件大?。?/td> 0K
描述: IC PLD ISP 32I/O 20NS 44PLCC
標準包裝: 26
系列: ispLSI® 1000
可編程類型: 系統(tǒng)內(nèi)可編程
最大延遲時間 tpd(1): 20.0ns
電壓電源 - 內(nèi)部: 4.5 V ~ 5.5 V
邏輯元件/邏輯塊數(shù)目: 16
門數(shù): 2000
輸入/輸出數(shù): 32
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 44-LCC(J 形引線)
供應商設備封裝: 44-PLCC(16.58x16.58)
包裝: 管件
其它名稱: ISPLSI1016-60LJI
ispLSI 1016
In-System Programmable High Density PLD
1
Functional Block Diagram
CLK
A0
A1
A2
A3
A4
A5
A6
A7
B
7
B
6
B
5
B
4
B
3
B
2
B
1
B
0
Output
Routing
Pool
Output
Routing
Pool
Global Routing Pool (GRP)
Logic
Array
DQ
GLB
Description
The ispLSI 1016 is a High-Density Programmable Logic
Device containing 96 Registers, 32 Universal I/O pins,
four Dedicated Input pins, three Dedicated Clock Input
pins and a Global Routing Pool (GRP). The GRP pro-
vides complete interconnectivity between all of these
elements. The ispLSI 1016 features 5-Volt in-system
programming and in-system diagnostic capabilities. It is
the first device which offers non-volatile reprogrammability
of the logic, as well as the interconnect to provide truly
reconfigurable systems.
The basic unit of logic on the ispLSI 1016 device is the
Generic Logic Block (GLB). The GLBs are labeled A0, A1
.. B7 (see figure 1). There are a total of 16 GLBs in the
ispLSI 1016 device. Each GLB has 18 inputs, a
programmable AND/OR/XOR array, and four outputs
which can be configured to be either combinatorial or
registered. Inputs to the GLB come from the GRP and
dedicated inputs. All of the GLB outputs are brought back
into the GRP so that they can be connected to the inputs
of any other GLB on the device.
1016_10
Features
HIGH-DENSITY PROGRAMMABLE LOGIC
— High-Speed Global Interconnect
— 2000 PLD Gates
— 32 I/O Pins, Four Dedicated Inputs
— 96 Registers
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
— Security Cell Prevents Unauthorized Copying
HIGH PERFORMANCE E2CMOS TECHNOLOGY
fmax = 110 MHz Maximum Operating Frequency
fmax = 60 MHz for Industrial and Military/883 Devices
tpd = 10 ns Propagation Delay
— TTL Compatible Inputs and Outputs
— Electrically Erasable and Reprogrammable
— Non-Volatile E2CMOS Technology
— 100% Tested
IN-SYSTEM PROGRAMMABLE
— In-System Programmable (ISP) 5-Volt Only
— Increased Manufacturing Yields, Reduced Time-to-
Market, and Improved Product Quality
— Reprogram Soldered Devices for Faster Debugging
COMBINES EASE OF USE AND THE FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEX-
IBILITY OF FIELD PROGRAMMABLE GATE ARRAYS
— Complete Programmable Device Can Combine Glue
Logic and Structured Designs
— Three Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
Copyright 2002 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
January 2002
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
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