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參數(shù)資料
| 型號： | ISPGDX80A-5T100 |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | 數(shù)字信號處理外設 |
| 英文描述： | In-System Programmable Generic Digital CrosspointTM |
| 中文描述： | DSP-CROSSBAR SWITCH, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁數(shù)： | 1/25頁 |
| 文件大?。?/td> | 326K |
| 代理商： | ISPGDX80A-5T100 |
ispGDX
TM
Family
In-System Programmable
Generic Digital Crosspoint
TM
ispgdx_08
1
Functional Block Diagram
Features
IN-SYSTEM PROGRAMMABLE GENERIC DIGITAL
CROSSPOINT FAMILY
— Advanced Architecture Addresses Programmable
PCB Interconnect, Bus Interface Integration and
Jumper/Switch Replacement
— Three Device Options: 80 to 160 Programmable I/O
Pins
— “Any Input to Any Output” Routing
— Fixed HIGH or LOW Output Option for Jumper/DIP
Switch Emulation
— Space-Saving TQFP, PQFP and BGA Packaging
— Dedicated IEEE 1149.1-Compliant Boundary Scan
Test
— PCI Compliant Output Drive
HIGH PERFORMANCE E
2
CMOS
TECHNOLOGY
— 5V Power Supply
— 5.0ns Input-to-Output/5.0ns Clock-to-Output Delay
— Low-Power: 40mA Quiescent Icc
— Balanced 24mA Output Buffers with Programmable
Slew Rate Control
— Schmitt Trigger Inputs for Noise Immunity
— Electrically Erasable and Reprogrammable
— Non-Volatile E
2
CMOS Technology
— 100% Tested
ispGDX OFFERS THE FOLLOWING ADVANTAGES
— In-System Programmable
— Lattice ISP or JTAG Programming Interface
— Only 5V Power Supply Required
— Change Interconnects in Seconds
— Reprogram Soldered Devices
FLEXIBLE ARCHITECTURE
— Combinatorial/Latched/Registered Inputs or Outputs
— Individual I/O Tri-state Control with Polarity Control
— Dedicated Clock Input Pins (two or four) or
Programmable Clocks from I/O Pins (from 20 up to
40)
— Up to 4:1 Dynamic Path Selection
— Programmable Output Pull-up Resistors
— Outputs Tri-state During Power-up (“Live Insertion”
Friendly)
DESIGN SUPPORT THROUGH LATTICE’S ispGDX
DEVELOPMENT SOFTWARE
— MS Windows or NT / PC-Based or Sun O/S
— Easy Text-Based Design Entry
— Automatic Signal Routing
— Program up to 100 ISP Devices Concurrently
— Simulator Netlist Generation for Easy Board-Level
Simulation
Global Routing
Pool
(GRP)
I/O
Cells
I/O Pins B
Boundary
Scan
Control
I/O
Cells
ISP
Control
I
I
I/O Pins D
Description
The ispGDX architecture provides a family of fast, flexible
programmable devices to address a variety of system-
level digital signal routing and interface requirements
including:
Multi-Port Multiprocessor Interfaces
Wide Data and Address Bus Multiplexing
(e.g. 4:1 High-Speed Bus MUX)
Programmable Control Signal Routing
(e.g. Interrupts, DMAREQs, etc)
Board-Level PCB Signal Routing for Prototyping or
Programmable Bus Interfaces
The ispGDX Family consists of three members with 80,
120 and 160 Programmable I/Os. These devices are
available in packages ranging from the 100-pin TQFP to
the 208-pin PQFP. The devices feature fast operation,
with input-to-output signal delays (Tpd) of 5ns and clock-
to-output delays of 5ns.
The architecture of the devices consists of a series of
programmable I/O cells interconnected by a Global Rout-
Copyright 2000 Lattice Semiconductor Corporation. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein
are subject to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
August 2000
相關PDF資料 |
PDF描述 |
|---|---|
| ISPGDX120A-7Q160 | In-System Programmable Generic Digital CrosspointTM |
| ISPGDX160A-7Q208 | In-System Programmable Generic Digital CrosspointTM |
| ISPGDX160-7Q208 | Electrical Outlet Connector; Contact Plating:Nickel; Current Rating:30A RoHS Compliant: Yes |
| ISPGDX120A-5T176 | Aluminum Electrolytic Radial Lead High Ripple, Long Life Capacitor; Capacitance: 15uF; Voltage: 400V; Case Size: 12.5x20 mm; Packaging: Bulk |
| ISPGDX120A-7T176 | Aluminum Electrolytic Radial Lead High Ripple, Long Life Capacitor; Capacitance: 22uF; Voltage: 400V; Case Size: 12.5x20 mm; Packaging: Bulk |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ISPGDX80A-7T100 | 功能描述:模擬和數(shù)字交叉點 IC PROGRAMMABLE GEN DIG CROSSPOINT RoHS:否 制造商:Micrel 配置:2 x 2 封裝 / 箱體:MLF-16 數(shù)據(jù)速率:10.7 Gbps 輸入電平:CML, LVDS, LVPECL 輸出電平:CML 電源電壓-最大:3.6 V 電源電壓-最小:2.375 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 產品:Digital Crosspoint 封裝:Tube |
| ISPGDX80VA-3T100 | 功能描述:模擬和數(shù)字交叉點 IC 3.3V 80 I/O RoHS:否 制造商:Micrel 配置:2 x 2 封裝 / 箱體:MLF-16 數(shù)據(jù)速率:10.7 Gbps 輸入電平:CML, LVDS, LVPECL 輸出電平:CML 電源電壓-最大:3.6 V 電源電壓-最小:2.375 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 產品:Digital Crosspoint 封裝:Tube |
| ISPGDX80VA3T100-5I | 制造商:Lattice Semiconductor Corporation 功能描述: |
| ISPGDX80VA-3TN100 | 功能描述:模擬和數(shù)字交叉點 IC PROGRAMMABLE GEN DIG CROSSPOINT RoHS:否 制造商:Micrel 配置:2 x 2 封裝 / 箱體:MLF-16 數(shù)據(jù)速率:10.7 Gbps 輸入電平:CML, LVDS, LVPECL 輸出電平:CML 電源電壓-最大:3.6 V 電源電壓-最小:2.375 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 產品:Digital Crosspoint 封裝:Tube |
| ISPGDX80VA5T100 | 制造商:Lattice Semiconductor Corporation 功能描述: |
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