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參數(shù)資料
| 型號： | ISPGAL22V10B-10LJ |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | PLD |
| 英文描述： | In-System Programmable E2CMOS PLD |
| 中文描述： | EE PLD, 10 ns, PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁數(shù)： | 11/15頁 |
| 文件大?。?/td> | 247K |
| 代理商： | ISPGAL22V10B-10LJ |
Specifications
ispGAL22V10
11
POWER-UP RESET
Vcc (min.)
t
pr
Internal Register
Reset to Logic "0"
Device Pin
Reset to Logic "1"
t
wl
t
su
Device Pin
Reset to Logic "0"
Vcc
CLK
INTERNAL REGISTER
Q - OUTPUT
ACTIVE LOW
OUTPUT REGISTER
ACTIVE HIGH
OUTPUT REGISTER
asynchronous nature of system power-up, some conditions must
be met to provide a valid power-up reset of the ispGAL22V10.
First, the Vcc rise must be monotonic. Second, the clock input
must be at static TTL level as shown in the diagram during power
up. The registers will reset within a maximum of
tpr time. As in nor-
mal system operation, avoid clocking the device until all input and
feedback path setup times have been met. The clock must also
meet the minimum pulse width requirements.
Output
Input
(Vref Typical = 3.2V)
Vcc
PIN
Vref
Tri-State
Control
Active Pull-up
Circuit
Feedback
(To Input Buffer)
PIN
Feedback
Data
Output
(Vref Typical = 3.2V)
Vcc
PIN
Vcc
Vref
Active Pull-up
Circuit (Except SDI
on ispGAL22V10C)
ESD
Protection
Circuit
ESD
Protection
Circuit
Vcc
PIN
Pull-down Resistor
(SDI on ispGAL22V10C Only)
INPUT/OUTPUT EQUIVALENT SCHEMATICS
Circuitry within the ispGAL22V10 provides a reset signal to all reg-
isters during power-up. All internal registers will have their Q out-
puts set low after a specified time (tpr, 1
μ
s MAX). As a result, the
state on the registered output pins (if they are enabled) will be
either high or low on power-up, depending on the programmed
polarity of the output pins. This feature can greatly simplify state
machine design by providing a known state on power-up. The
timing diagram for power-up is shown below. Because of the
相關PDF資料 |
PDF描述 |
|---|---|
| ISPGAL22V10B-15LJ | 16-Wide LVDS Receiver w/Integrated Termination |
| ISPGAL22V10 | In-System Programmable E2CMOS PLD |
| ISPGAL22V10B-7LJ | In-System Programmable E2CMOS PLD |
| ISPGAL22V10C-15LJ | In-System Programmable E2CMOS PLD |
| ISPGAL22V10C-15LJI | In-System Programmable E2CMOS PLD |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ISPGAL22V10B-15LJ | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable E2CMOS PLD |
| ISPGAL22V10B-7LJ | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable E2CMOS PLD |
| ISPGAL22V10C-10LJ | 功能描述:SPLD - 簡單可編程邏輯器件 5V 22 I/O RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風格:Through Hole 封裝 / 箱體:DIP-24 |
| ISPGAL22V10C-10LJI | 制造商:Lattice Semiconductor Corporation 功能描述: |
| ISPGAL22V10C-10LJN | 功能描述:SPLD - 簡單可編程邏輯器件 PROGRAMMABLE LO VOLT E2CMOS PLD RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風格:Through Hole 封裝 / 箱體:DIP-24 |
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