參數(shù)資料
型號(hào): ISP1583
廠商: NXP Semiconductors N.V.
英文描述: Hi-Speed Universal Serial Bus peripheral controller
中文描述: 高速通用串行總線(xiàn)外設(shè)控制器
文件頁(yè)數(shù): 49/87頁(yè)
文件大?。?/td> 420K
代理商: ISP1583
Philips Semiconductors
ISP1583
Hi-Speed USB peripheral controller
Product data
Rev. 03 — 12 July 2004
49 of 87
9397 750 13461
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
[1]
The DREQ pin will be driven only after performing a write access to the DMA Configuration register
(that is, after configuring the DMA Configuration register).
PIO read or write that started using DMA Command register only performs 16-bit transfer.
[2]
9.4.4
DMA Hardware register (address: 3Ch)
The DMA Hardware register consists of 1 byte. The bit allocation is shown in
Table 56
.
This register determines the polarity of the bus control signals (EOT, DACK, DREQ,
DIOR and DIOW) and DMA mode (master or slave). It also controls whether the
upper and lower parts of the data bus are swapped (bits ENDIAN[1:0]), for modes
GDMA (slave) and MDMA (master) only.
3 to 2
MODE[1:0]
These bits only affect the GDMA (slave) and MDMA (master)
handshake signals.
00 —
DIOR (master) or DIOW (slave): strobes data from the
DMA bus into the ISP1583; DIOW (master) or DIOR (slave):
puts data from the ISP1583 on the DMA bus.
01 —
DIOR (master) or DACK (slave): strobes the data from
the DMA bus into the ISP1583; DACK (master) or DIOR
(slave): puts the data from the ISP1583 on the DMA bus.
10 —
DACK (master and slave): strobes the data from the
DMA bus into the ISP1583 and also puts the data from the
ISP1583 on the DMA bus (This mode is applicable only to the
16-bit DMA; this mode cannot be used for the 8-bit DMA.).
11 —
reserved.
reserved
This bit selects the DMA bus width for GDMA (slave) and
MDMA (master).
1
0
-
WIDTH
0 —
8-bit data bus.
1 —
16-bit data bus.
Table 55:
Bit
DMA Configuration register: bit description
[1]
…continued
Symbol
Description
Table 56:
Bit
Symbol
DMA Hardware register: bit allocation
7
ENDIAN[1:0]
6
5
4
3
2
1
0
EOT_POL
MASTER
ACK_POL
DREQ_
POL
1
1
R/W
WRITE_
POL
0
0
R/W
READ_
POL
0
0
R/W
Reset
Bus reset
Access
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
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