參數(shù)資料
型號： ISP1581
廠商： NXP Semiconductors N.V.
英文描述： Universal Serial Bus 2.0 high-speed interface device
中文描述： 通用串行總線2.0高速接口設(shè)備
文件頁數(shù)： 16/73頁
文件大小： 1819K
代理商： ISP1581
Philips Semiconductors
ISP1581
USB 2.0 HS interface device
Objective specification
Rev. 02 — 23 October 2000
16 of 73
9397 750 07648
Philips Electronics N.V. 2000. All rights reserved.
9.2.4
Interrupt Enable register (address: 14H)
This register enables/disables individual interrupt sources. The interrupt for each
endpoint can be individually controlled via the associated IEPnRX or IEPnTX bits (‘n’
representing the endpoint number). All interrupts can be globally disabled via bit
GLINTENA in the Mode Register (see
Table 7
).
An interrupt is generated when the USB SIE receives or generates an ACK, NAK or
STALL on the USB bus. The interrupt generation depends on the Debug mode
settings of bit fields CDBGMOD, DDBGMODIN and DDBGMODOUT.
All data IN transactions use the Transmit buffers (TX), which are handled by the
DDBGMODIN bits. All data OUT transactions go via the Receive buffers (RX), which
are handled by the DDBGMODOUT bits. Transactions on Control endpoint 0 (IN,
OUT and SETUP) are handled by the CDBGMOD bits.
Interrupts caused by events on the USB bus (SOF, Pseudo SOF, suspend, resume,
bus reset, Setup and High Speed Status) can also be controlled individually. A bus
reset disables all enabled interrupts except bit IEBRST (bus reset), which remains
unchanged.
The Interrupt Enable Register consists of 4 bytes. The bit allocation is given in
Table 12
.
Table 12: Interrupt Enable register: bit allocation
Bit
31
Symbol
reserved
Reset
0
Bus Reset
0
Access
R/W
Bit
23
Symbol
IEP6TX
Reset
0
Bus Reset
0
Access
R/W
Bit
15
Symbol
IEP2TX
Reset
0
Bus Reset
0
Access
R/W
Bit
7
Symbol
reserved
Reset
0
Bus Reset
0
Access
R/W
30
29
28
27
26
25
24
reserved
0
0
R/W
22
IEP6RX
0
0
R/W
14
IEP2RX
0
0
R/W
6
IEDMA
0
0
R/W
reserved
0
0
R/W
21
IEP5TX
0
0
R/W
13
IEP1TX
0
0
R/W
5
IEHS_STA
0
0
R/W
reserved
0
0
R/W
20
IEP5RX
0
0
R/W
12
IEP1RX
0
0
R/W
4
IERESM
0
0
R/W
reserved
0
0
R/W
19
IEP4TX
0
0
R/W
11
IEP0TX
0
0
R/W
3
IESUSP
0
0
R/W
reserved
0
0
R/W
18
IEP4RX
0
0
R/W
10
IEP0RX
0
0
R/W
2
IEPSOF
0
0
R/W
IEP7TX
0
0
R/W
17
IEP3TX
0
0
R/W
9
reserved
0
0
R/W
1
IESOF
0
0
R/W
IEP7RX
0
0
R/W
16
IEP3RX
0
0
R/W
8
IEP0SETUP
0
0
R/W
0
IEBRST
0
unchanged
R/W
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