參數(shù)資料
型號: ISP1562
廠商: NXP Semiconductors N.V.
英文描述: Hi-Speed Universal Serial Bus PCI Host Controller
中文描述: 高速通用串行總線PCI主機控制器
文件頁數(shù): 60/98頁
文件大小: 442K
代理商: ISP1562
9397 750 14223
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 14 July 2005
60 of 98
Philips Semiconductors
ISP1562
USB PCI Host Controller
8
PPS
On read—
PortPowerStatus
: This bit reflects the port power status,
regardless of the type of power switching implemented. This bit is cleared if
an overcurrent condition is detected. The HCD can set this bit by writing
SetPortPower or SetGlobalPower. The HCD can clear this bit by writing
ClearPortPower or ClearGlobalPower. PowerSwitchingMode and
PortPowerControlMask[NDP] determine which power control switches are
enabled. In global switching mode (PowerSwitchingMode = 0), only
Set/ClearGlobalPower controls this bit. In the per-port power switching
(PowerSwitchingMode = 1), if the PortPowerControlMask[NDP] bit for the
port is set, only Set/ClearPortPower commands are enabled. If the mask is
not set, only Set/ClearGlobalPower commands are enabled.
When port power is disabled, bits CCS (CurrentConnectStatus), PES
(PortEnableStatus), PSS (PortSuspendStatus) and PRS (PortResetStatus)
should be reset.
0 —
Port power is off
1 —
Port power is on.
On write—
SetPortPower
: The HCD can write logic 1 to set the PPS
(PortPowerStatus) bit. Writing logic 0 has no effect.
Remark:
This bit always reads logic 1 if power switching is not supported.
-
On read—
PortResetStatus
: When this bit is set by a write to SetPortReset,
port reset signaling is asserted. When reset is completed and PRSC is set,
this bit is cleared.
0 —
Port reset signal is inactive
1 —
Port reset signal is active.
On write—
SetPortReset
: The HCD can set the port reset signaling by
writing logic 1 to this bit. Writing logic 0 has no effect. If CCS is cleared, this
write does not set PRS (PortResetStatus) but instead sets CCS. This
informs the driver that it attempted to reset a disconnected port.
On read—
PortOverCurrentIndicator
: This bit is valid only when the Root
Hub is configured to show overcurrent conditions are reported on a per-port
basis. If the per-port overcurrent reporting is not supported, this bit is set to
logic 0. If cleared, all power operations are normal for this port. If set, an
overcurrent condition exists on this port.
0 —
No overcurrent condition
1 —
Overcurrent condition detected.
On write—
ClearSuspendStatus
: The HCD can write logic 1 to initiate a
resume. Writing logic 0 has no effect. A resume is initiated only if PSS
(PortSuspendStatus) is set.
7 to 5
4
reserved
PRS
3
POCI
Table 85:
HcRhPortStatus[4:1] - Host Controller Root Hub Port Status[4:1] register bit
description
…continued
Address: Value read from func0 or func1 of address 10h + 54h
Bit
Symbol
Description
相關PDF資料
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