參數(shù)資料
型號: ISP1362EE
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Single-chip Universal Serial Bus On-The-Go controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PBGA64
封裝: 6 X 6 MM, 0.80 HEIGHT, PLASTIC, MO-195, SOT-543-1, TFBGA-64
文件頁數(shù): 120/150頁
文件大?。?/td> 647K
代理商: ISP1362EE
Philips Semiconductors
ISP1362
Single-chip USB OTG controller
Product data
Rev. 03
06 January 2004
120 of 150
9397 750 12337
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Code (Hex): 01 to 0F
write (control IN, endpoint 1 to 14)
Code (Hex): 10, 12 to 1F
read (control OUT, endpoint 1 to 14)
Transaction
write or read maximum N
+
2 bytes (isochronous endpoint: N
1023,
bulk/interrupt endpoint: N
32) (code or data)
The data in the endpoint buffer memory must be organized as shown in
Table 122
. An
example of endpoint buffer memory access is given in
Table 123
.
Remark:
There is no protection against writing or reading past a buffer
s boundary,
against writing into an OUT buffer or reading from an IN buffer. Any of these actions
could cause an incorrect operation. Data residing in an OUT buffer is only meaningful
after a successful transaction. Exception: during DMA access of a double-buffered
endpoint, the buffer pointer automatically points to the secondary buffer after
reaching the end of the primary buffer.
16.2.2
Read Endpoint Status (R: 50H
5FH)
This command is used to read the status of an endpoint buffer memory. The
command accesses the DcEndpointStatus register, the bit allocation of which is
shown in
Table 124
. Reading the DcEndpointStatus register will clear the interrupt bit
set for the corresponding endpoint in the DcInterrupt register (see
Table 140
).
All bits of the DcEndpointStatus register are read-only. Bit EPSTAL is controlled by
the Stall or Unstall commands and by the reception of a SET-UP token (see
Section 16.2.3
).
Code (Hex): 50 to 5F
read (control OUT, control IN, endpoint 1 to 14)
Transaction
read 1 byte (code only)
Table 122: Endpoint buffer memory organization
Word #
0 (lower byte)
0 (upper byte)
1 (lower byte)
1 (upper byte)
M = (N + 1)/2
Description
packet length (lower byte)
packet length (upper byte)
data byte 1
data byte 2
data byte N
Table 123: Example of endpoint buffer memory access
A0
Phase
Bus lines
HIGH
command
D[7:0]
D[15:8]
LOW
data
D[15:0]
LOW
data
D[15:0]
LOW
data
D[15:0]
Word #
-
-
0
1
2
Description
command code (00H to 1FH)
ignored
packet length
data word 1 (data byte 2, data byte 1)
data word 2 (data byte 4, data byte 3)
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