參數(shù)資料
型號： ISP1130N
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： Universal Serial Bus compound hub with integrated keyboard controller
中文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PDIP56
封裝： PLASTIC, SDIP-56
文件頁數(shù)： 38/68頁
文件大?。?/td> 1786K
代理商： ISP1130N
Philips Semiconductors
ISP1130
USB compound hub with keyboard controller
Objective specification
Rev. 01 — 23 March 2000
38 of 68
9397 750 06895
Philips Electronics N.V. 2000. All rights reserved.
10.3.4
USB Control A register (USBCONA)
Table 54: USBCON register: bit description
Bit
Symbol
7
Self
Powered
6
Enable
SYNCLK
Description
A logic 0 selects bus-powered operation. A logic 1 enables (hybrid)
self-powered operation.
A logic 1 enables a 12 MHz clock signal on output SYNCLK, used
during external emulation of the microcontroller. A logic 0 disables
the clock signal on SYNCLK.
A logic 0 selects internal 82 k
pull-down resistors on the MYn
lines (keyboard matrix enabled). A logic 1 selects internal 8.2 k
pull-up resistors on the MYn lines (keyboard matrix disabled).
A logic 0 enables upstream GoodLink indication, using output
MEMSEL/UPGL to drive the LED. A logic 1 configures pin
MEMSEL/UPGL as a chip select output for accessing an external
serial EEPROM via the I
2
C-bus interface.
A logic 1 configures pins OCn/DPGLn as overcurrent detection
inputs. A logic 0 configures pins OCn/DPGLn as downstream port
GoodLink indicator outputs.
A logic 0 enables internal analog overcurrent sensing on pins
OCn/DPGLn (if enabled via bit EnableOverCurrent). A logic 1
selects digital overcurrent sensing.
A logic 0 connects an internal 1.5 k
pull-up resistor to the
upstream USB port (pin UP_DP). A logic 1 disables the pull-up
resistor.
A logic 1 switches off the clock after 2 ms following a ‘suspend’
interrupt. A logic 0 causes the clock to remain active during
‘suspend’ state. A change from logic 0 to logic 1 in the ‘suspend’
interrupt service routine switches off the clock after 1 ms.
5
Disable
KBDMatrix
4
GL-
MEMSEL
Selection
3
Enable
Over
Current
AnalogOC
Disable
2
1
Soft
Connect_N
0
Suspend
Clock
Table 55: USBCONA register: bit allocation
Bit
7
Symbol
Reset
0
Access
W
6
5
4
3
2
1
0
reserved
PortCount1
0
W
PortCount0
1
W
0
W
0
W
0
W
0
W
0
W
Table 56: USBCONA register: bit description
Bit
Symbol
7 to 2
-
1, 0
PortCount[1:0] number of enabled embedded functions:
00 —
undefined
01 —
1 embedded function (default)
10 —
2 embedded functions
11 —
3 embedded functions
Description
reserved
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相關代理商/技術參數(shù)
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