參數(shù)資料
型號(hào): ISO806
廠商: Texas Instruments, Inc.
英文描述: Isolated 12-Bit Sampling Analog-To-Digital Converter(隔離的12位采樣A\D轉(zhuǎn)換器)
中文描述: 隔離12位采樣模擬到數(shù)字轉(zhuǎn)換器(隔離的12位采樣阿\\?轉(zhuǎn)換器)
文件頁(yè)數(shù): 7/12頁(yè)
文件大小: 201K
代理商: ISO806
7
ISO806
STARTING A CONVERSION
The R/C (pin 1) LOW for a minimum of 40ns immediately
puts the sample/hold of the ISO806 in the hold state and
starts conversion ‘n’. BUSY (pin 2) will go LOW and stay
LOW until conversion ‘n’ is completed and the internal
output register has been updated. All new convert com-
mands during BUSY LOW will be ignored. R/C must go
HIGH before BUSY goes HIGH or a new conversion will be
initiated without sufficient time to acquire a new signal.
The ISO806 will begin tracking the input signal at the end
of the conversion. Allowing 25
μ
s between convert com-
mands assures accurate acquisition of a new signal. R/C is
level triggered.
READING DATA
The ISO806 outputs serial data in Straight Binary or Binary
Two’s Complement data output format. If SB/BTC (pin 18)
is HIGH, the output will be in SB format, and if LOW, the
output will be in BTC format. Refer to Table IV for ideal
output codes.
Reading the data through the serial port will shift the internal
output registers one bit per data clock pulse.
BASIC OPERATION
SERIAL OUTPUT
Figure 1 shows a basic circuit to operate the ISO806 with a
±
10V input range and serial output. Taking R/C (pin 1)
LOW for 40ns (12
μ
s max) will initiate a conversion and
output valid data from the previous conversion on SDATA
(pin 28) synchronized to 12 clock pulses output on
DATACLK (pin 27). BUSY (pin 2) will go LOW and stay
LOW until the conversion is completed and the serial data
has been transmitted. Data will be output in Binary Two’s
Complement format, MSB first, and will be valid on both the
rising and falling edges of the data clock. BUSY going
HIGH can be used to latch the data. All convert commands
will be ignored while BUSY is LOW.
The ISO806 will begin tracking the input signal at the end
of the conversion. Allowing 25
μ
s between convert com-
mands assures accurate acquisition of a new signal.
The offset and gain are adjusted internally to allow external
trimming with a single supply. The external resistors com-
pensate for this adjustment and can be left out if the offset
and gain will be corrected in software (refer to the
Calibra-
tion
section).
FIGURE 1. Basic
±
10V Operation with Serial Output.
DESCRIPTION
ANALOG INPUT
Full-Scale Range
Least Significant Bit (LSB)
±
10
0V to 5V
1.22mV
0V to 4V
976
μ
V
4.88mV
DIGITAL OUTPUT
HEX
HEX
BINARY CODE
CODE
BINARY CODE
CODE
+Full Scale (FS – 1LSB)
9.99512V
4.99878V
3.999024V
0111 1111 1111
7FF
1111 1111 1111
FFF
Midscale
0V
2.5V
2V
0000 0000 0000
000
1000 0000 0000
800
One LSB Below Midscale
–4.88mV
2.49878V
1.999024V
1111 1111 1111
FFF
0111 1111 1111
7FF
–Full Scale
–10V
0V
0V
1000 0000 0000
800
0000 0000 0000
000
BINARY TWO’S COMPLEMENT
(SB/BTC LOW)
STRAIGHT BINARY
(SB/BTC HIGH)
SYMBOL
DESCRIPTION
MIN
TYP
MAX UNITS
t
1
Convert Pulse Width
0.04
12
μ
s
t
3
BUSY Delay from
Start of Conversion
110
ns
t
4
BUSY LOW
14.7
20
μ
s
t
5
BUSY Delay after
End of Conversion
90
ns
t
6
Aperture Delay
40
ns
t
7
Conversion Time
14.7
20
μ
s
t
8
Acquisition Time
3
μ
s
t
13
Start of Conversion
to DATACLK Delay
1.4
μ
s
t
14
DATACLK Period
1.1
μ
s
t
15
Data Valid to DATACLK
HIGH Delay
75
ns
t
16
Data Valid after DATACLK
LOW Delay
600
ns
t
7
+ t
8
Throughput Time
25
μ
s
TABLE V. Conversion and Data Timing. T
A
= –40
°
C to +85
°
C.
SDATA
DATACLK
DGND2
DGND1
SB/BTC
AGND
REF
CAP
R/C
BUSY
+5V
DIG2
+5V
DIG1
+5V
ANA
R1
IN
NC
R2
IN
1
2
3
10
11
12
13
14
28
27
26
19
18
17
16
15
ISO806
200
100
10
μ
F
2.2
μ
F
+
2.2
μ
F
+5V
+5V
V
IN
66.5k
+5V
0.1
μ
F
+
Table IV. Output Codes and Ideal Input Voltages.
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