參數(shù)資料
型號: ISL98003CNZ-EVALZ
廠商: Intersil
文件頁數(shù): 6/31頁
文件大小: 0K
描述: EVAL BOARD FOR ISL98003CNZ
標(biāo)準(zhǔn)包裝: 1
系列: *
14
FN6760.0
September 12, 2008
0x27
ABLC Configuration, (0x40)
0
ABLC Disable
0: ABLC on (default) - use 8-bit digital offset control.
0x000 = -0x200 LSB offset, 0x3FF = +0x1FF LSB offset,
0x200 = 0x000 LSB offset.
1: ABLC off - use 8-bit offset DACs, bypass digital adder
(add/subtract nothing, but keep same delay through
channel).
1
Offset DAC Range
0: ±1/2 ADC fullscale (1 LSB = 0.25 ADC LSBs)
1: ±1/4 ADC fullscale (1 LSB = 0.165 ADC LSBs)
3:2
ABLC Pixel Width
Number of black pixels averaged every line for ABLC function
00: 16 pixels [default]
01: 32 pixels
10: 64 pixels
11: 128 pixels
6:4
ABLC Bandwidth
ABLC Time constant (lines) = 2([5+6:4])
000 = 32 lines
100 = 512 lines (default)
111 = 4096 lines
0x28
Output Format 1, (0x00)
0
Data Output Format
0: 4:4:4 (24-bit output)
1: 4:2:2 (16-bit output on G and R)
1
4:2:2 Order
0: First pixel on R channel is U
1: First pixel on R channel is V
2
4:2:2 Processing
0: U, V filtered (high quality)
1: Odd U, V pixels dropped (lower quality)
3
8-bit Mode
Should be set to 1
5:4
Oversampling
00: Normal operation (1x sampling)
01:2x oversampling, 2 samples averaged at ADC output
10:4x oversampling, 4 samples averaged at ADC output
11:8x oversampling, 8 samples averaged at ADC output
In Oversampling mode, the HTOTAL, DC-Restore/ABLC Start,
DC-Restore Width, and ABLC width values are automatically
multiplied by the oversampling ratio. The pixel clock is divided
by the oversampling ratio when the data is decimated.
Decimator is reset on trailing edge of HSYNC.
6
RGB2YUV Color Space
Conversion Enable
0: CSC Disabled
1: CSC Enabled
Note: The data delay through the entire AFE is identical with
CSC on and CSC off.
Register Listing (Continued)
ADDRESS
REGISTER
(DEFAULT VALUE)
BITS
FUNCTION NAME
DESCRIPTION
ISL98003
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