參數(shù)資料
型號(hào): ISL98001CQZ-170
廠商: INTERSIL CORP
元件分類: 消費(fèi)家電
英文描述: Triple Video Digitizer with Digital PLL
中文描述: SPECIALTY CONSUMER CIRCUIT, PQFP128
封裝: 14 x 20 MM, ROHS COMPLIANT, PLASTIC, MS-022, MQFP-128
文件頁數(shù): 15/29頁
文件大小: 470K
代理商: ISL98001CQZ-170
15
FN6148.0
October 25, 2005
0x13
PLL Misc (0x04)
0
PLL Lock Edge
HSYNC1
0: Lock on trailing edge of HSYNC1 (default)
1: Lock on leading edge of HSYNC1
1
PLL Lock Edge
HSYNC2
0: Lock on trailing edge of HSYNC2 (default)
1: Lock on leading edge of HSYNC2
2
Reserved
Set to 0
3
CLKINV
IN
Pin
Disable
0: CLKINV
IN
pin enabled (default)
1: CLKINV
IN
pin disabled (internally forced low)
5:4
CLKINV
IN
Pin
Function
00: CLKINV (default)
01: External CLAMP (See Note)
10: External COAST
11: External PIXCLK
Note: the CLAMP pulse is used to
- perform a DC restore (if enabled)
- start the ABLC function (if enabled), and
- update the data to the Offset DACs (always).
In the default internal CLAMP mode, the ISL98001
automatically generates the CLAMP pulse. If External
CLAMP is selected, the Offset DAC values only
change on the leading edge of CLAMP. If there is no
internal clamp signal, there will be up to a 100ms
delay between when the PGA gain or offset DAC
register is written to, and when the PGA or offset DAC
is actually updated.
6
XCLK
OUT
Frequency
0: XCLK
OUT
= f
CRYSTAL
(default)
1: XCLK
OUT
= f
CRYSTAL
/2
7
Disable XCLK
OUT
0 = XCLK
OUT
enabled
1 = XCLK
OUT
is logic low
0x14
DC Restore and ABLC starting pixel
MSB (0x00)
4:0
DC Restore and
ABLC starting
pixel (MSB)
Pixel after HSYNC
IN
trailing edge to begin
DC restore and ABLC functions. 13-bits.
Set this register to the first stable black pixel following
the trailing edge of HSYNC
IN
.
0x15
DC Restore and ABLC starting pixel LSB
(0x03)
7:0
DC Restore and
ABLC starting
pixel (LSB)
0x16
DC Restore Clamp Width
(0x10)
7:0
DC Restore clamp
width (pixels)
Width of DC restore clamp used in AC-coupled
configurations. Has no effect on ABLC. Minimum
value is 0x02 (a setting of 0x01 or 0x00 will not
generate a clamp pulse).
0x17
ABLC Configuration (0x40)
0
ABLC disable
0: ABLC enabled (default)
1: ABLC disabled
1
Reserved
Set to 0.
3:2
ABLC pixel width
Number of black pixels averaged every line for
ABLC function
00: 16 pixels [default]
01: 32 pixels
10: 64 pixels
11: 128 pixels
6:4
ABLC bandwidth
ABLC Time constant (lines) = 2
(5+[6:4])
000 = 32 lines
100 = 256 lines (default)
111 = 4096 lines
7
Reserved
Set to 0.
Register Listing
(Continued)
ADDRESS
REGISTER (DEFAULT VALUE)
BIT(S)
FUNCTION NAME
DESCRIPTION
ISL98001
相關(guān)PDF資料
PDF描述
ISL98001CQZ-140 Triple Video Digitizer with Digital PLL
ISL98001CQZ-210 Triple Video Digitizer with Digital PLL
ISL98001CQZ-240 Triple Video Digitizer with Digital PLL
ISL98001CQZ-275 Triple Video Digitizer with Digital PLL
ISL98001 Triple Video Digitizer with Digital PLL
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