參數(shù)資料
型號(hào): ISL97652IRZ-TK
廠商: INTERSIL CORP
元件分類: 穩(wěn)壓器
英文描述: 4-Channel Integrated LCD Supply with Dual VCOM Amplifiers
中文描述: 2.5 A SWITCHING REGULATOR, 1500 kHz SWITCHING FREQ-MAX, PQCC48
封裝: 7 X 7 MM, ROHS COMPLIANT, PLASTIC, MO-220VKKD-2, QFN-48
文件頁(yè)數(shù): 22/25頁(yè)
文件大?。?/td> 709K
代理商: ISL97652IRZ-TK
22
FN9287.0
December 21, 2006
Switching Frequency Control
The ISL97652 can operate at either 650kHz or 1.3MHz
depending on the state of the FREQ pin. When connected to
GND, 650kHz is selected. When connected to V
IN
, 1.3MHz
is selected. Higher frequencies enable the selection of
smaller inductors and capacitors. Lower frequencies allow
closer input/output ratios to be supported. The charge pump
circuits switch at half the frequency selected.
Undervoltage Lockout
The integrated undervoltage lockout circuit is designed to
power down the TFT-LCD if the input voltage falls below a
preset threshold. The ISL97652 will not start if the input
voltage is below the UVLO threshold.
Over-Temperature Protection
An internal temperature sensor continuously monitors the
die temperature. In the event that the die temperature
exceeds the thermal trip point of +150°C, the device will shut
down. Operation with die temperatures between +125°C and
150°C can be tolerated for short periods of time, however, in
order to maximize the operating life of the IC, it is
recommended that the effective continuous operating
junction temperature of the die should not exceed +125°C.
Fault Detection
The ISL97652 includes extensive fault handling circuitry,
which interacts with the start-up sequence circuitry if a fault
is detected.
During normal operation, if EN1 goes L, all major functions
are disabled immediately, including the 5V regulator. If EN2
goes L, but EN1 remains H, boost, V
ON
and GPM are
disabled immediately. When EN1 and/or EN2 return H, the
start-up sequence restarts from the appropriate point.
If the over-temperature threshold (+150°C nominal) is
exceeded, or if V
IN
drops below the specified lower UVLO
limit, all major functions are disabled immediately, excluding
the 5.3V regulator. If/when the temperature drops below
+100°C, or V
IN
returns to a level above the upper UVLO
threshold the start-up sequence will re-commence by
enabling REF.
Timed “Faults”
The four ramp voltages, SSB, SS, DEL1 and DEL2 all ramp
linearly from 0V to approximately 2.7V, where they are
soft-clamped. The 2V thresholds of each are used to enable
timed fault checking on related blocks. Therefore, external
capacitor values should be chosen such that all major
FIGURE 24. TIMING DIAGRAM 3
EN2
VDPM
V
MAIN
V
ON
A
VDD
VFLK
VGHM
V
IN
- DIODE
DLY2
V
IN
- DIODE OR
V
MAIN
DIODE
ISL97652
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