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參數(shù)資料
| 型號(hào)： | ISL97651ARTZ-T |
| 廠商： | INTERSIL CORP |
| 元件分類： | 顯示驅(qū)動(dòng)器 |
| 英文描述： | 4-Channel Integrated LCD Supply |
| 中文描述： | LIQUID CRYSTAL DISPLAY DRIVER, QCC36 |
| 封裝： | 6 X 6 MM, ROHS COMPLIANT, PLASTIC, MO-220WJJD-1, TQFN-36 |
| 文件頁數(shù)： | 16/19頁 |
| 文件大?。?/td> | 307K |
| 代理商： | ISL97651ARTZ-T |
16
FN7493.2
March 15, 2007
V
ON
Slice Circuit
The V
ON
Slice Circuit functions as a three way multiplexer,
switching the voltage on COM between ground, DRN and SRC,
under control of the start-up sequence and the CTL pin.
During the start-up sequence, COM is held at ground via an
NDMOS FET, with ~1k impedance. Once the start-up
sequence has completed, CTL is enabled and acts as a
multiplexer control such that if CTL is low, COM connects to
DRN through a 30
Ω
internal MOSFET, and if CTL is high,
COM connects to P
OUT
internally via a 5
Ω
MOSFET.
The slew rate of start-up of the switch control circuit is mainly
restricted by the load capacitance at COM pin as
Equation 21:
V
i
RWhere V
g
is the supply voltage applied to DRN or voltage
at P
OUT
, which range is from 0V to 36V. R
i
is the resistance
between COM and DRN or P
OUT
including the internal
MOSFET r
DS(On)
, the trace resistance and the resistor
inserted, R
L
is the load resistance of switch control circuit,
and C
L
is the load capacitance of switch control circuit.
In the “Typical Application Diagram” on page 10, R10, R11
and C15 give the bias to DRN based on Equation 22:
And R12 can be adjusted to adjust the slew rate.
Start-Up Sequence
Figure 15 shows a detailed start up sequence waveform. For
a successful power up, there should be 6 peaks at V
CDLY
.
When a fault is detected, the device will latch off until either
EN is toggled or the input supply is recycled.
When the input is higher than 2.75V; if either EN or ENL is H,
V
REF
turns on. If ENL is H, V
LOGIC
turns on. If EN is H, an
internal current source starts to charge C
CDLY
to an upper
threshold using a fast ramp followed by a slow ramp. Several
more ramps follow, during which time the device checks for
fault conditions. If a fault is found, the sequence is halted.
Initially the boost is not enabled so A
VDD
rises to
V
IN
- V
DIODE
through the output diode. Hence, there is a step
at A
VDD
during this part of the start up sequence. If this step is
not desirable, an external PMOS FET can be used to delay
the output until the boost is enabled internally. The delayed
output appears at A
VDD
.
A
VDD
soft-starts at the beginning of the third ramp. The soft-
start ramp depends on the value of the C
DLY
capacitor. The
range of C
DLY
capacitor value is from 10nF to 220nF. For
C
DLY
of 220nF, the soft-start time is ~8ms.
V
OFF
turns on at the start of the fourth peak, at the same time
DELB gate goes low to turn on the external PMOS to
generate a delayed A
VDD
output.
V
ON
is enabled at the beginning of the sixth ramp.
Once the start-up sequence is complete, the voltage on the
C
DLY
capacitor remains at 1.15V until either a fault is detected
or the EN pin is disabled. If a fault is detected, the voltage on
C
DLY
rises to 2.4V at which point the chip is disabled until the
power is cycled or enable is toggled.
V
Δ
t
-------
L
L
------------------------------------
=
(EQ. 21)
FIGURE 14. NEGATIVE CHARGE PUMP BLOCK DIAGRAM
FAULT
0.2V
CLK
EN
VDD
VSUP
FBN
NOUT
PGND
STOP
PWM
CONTROL
V
REF
R6
40k
C20
820pF
C19
100pF
R7
328k
V
OFF
(-8V)
C13
470nF
D2
D3
C12
220nF
A2
0.4V
A1
M1
M2
1.2MHz
V
DRN
V
R
+AVDD R
10
11
------------------------------+
=
(EQ. 22)
ISL97651
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