- 鎮ㄧ従(xi脿n)鍦ㄧ殑浣嶇疆锛�璨疯常IC缍�(w菐ng) > PDF鐩寗9423 > ISL95810UIU8Z-T (Intersil)IC POT DGTL 50K OHM 8-MSOP PDF璩囨枡涓嬭級
鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | ISL95810UIU8Z-T |
| 寤犲晢锛� | Intersil |
| 鏂囦欢闋佹暩(sh霉)锛� | 8/13闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC POT DGTL 50K OHM 8-MSOP |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 1 |
| 绯诲垪锛� | XDCP™ |
| 鎺ョ墖锛� | 256 |
| 闆婚樆锛堟瓙濮嗭級锛� | 50k |
| 闆昏矾鏁�(sh霉)锛� | 1 |
| 婧害绯绘暩(sh霉)锛� | 妯�(bi膩o)婧�(zh菙n)鍊� ±45 ppm/°C |
| 瀛樺劜(ch菙)鍣ㄩ鍨嬶細 | 闈炴槗澶� |
| 鎺ュ彛锛� | I²C |
| 闆绘簮闆诲锛� | 2.7 V ~ 5.5 V |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 8-TSSOP锛�8-MSOP锛�0.118"锛�3.00mm 瀵級 |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 8-MSOP |
| 鍖呰锛� | 妯�(bi膩o)婧�(zh菙n)鍖呰 |
| 鐢�(ch菐n)鍝佺洰閷勯爜闈細 | 1237 (CN2011-ZH PDF) |
| 鍏跺畠鍚嶇ū锛� | ISL95810UIU8Z-TDKR |
4
FN8090.2
September 19, 2006
ILkgDig
Leakage Current, at Pins SDA, SCL,
and WP Pins
Voltage at pin from GND to VCC
-10
10
A
tDCP (Note 13)
DCP Wiper Response Time
SCL falling edge of last bit of DCP Data Byte to
wiper change
1s
Vpor
Power-On Recall Voltage
Minimum VCC at which memory recall occurs
1.8
2.6
V
VCCRamp
VCC Ramp Rate
0.2
V/ms
tD (Note 13)
Power-Up Delay
VCC above Vpor, to DCP Initial Value Register recall
completed, and I2C Interface in standby state
3ms
EEPROM SPECIFICATIONS
EEPROM Endurance
200,000
Cycles
EEPROM Retention
Temperature
鈮� +75掳C
50
Years
SERIAL INTERFACE SPECIFICATIONS
VIL
WP, SDA, and SCL Input Buffer LOW
Voltage
-0.3
0.3*VCC
V
VIH
WP, SDA, and SCL Input Buffer
HIGH Voltage
0.7*VCC
VCC+0.3
V
Hysteresis (Note 13) SDA and SCL Input Buffer Hysteresis
0.05*VCC
V
VOL (Note 13)
SDA Output Buffer LOW Voltage,
Sinking 4mA
00.4
V
Cpin (Note 13)
WP, SDA, and SCL Pin Capacitance
10
pF
fSCL
SCL Frequency
400
kHz
tIN (Note 13)
Pulse Width Suppression Time at
SDA and SCL Inputs
Any pulse narrower than the max spec is
suppressed.
50
ns
tAA (Note 13)
SCL Falling Edge to SDA Output
Data Valid
SCL falling edge crossing 30% of VCC, until SDA
exits the 30% to 70% of VCC window.
900
ns
tBUF (Note 13)
Time the Bus Must be Free Before
the Start of a New Transmission
SDA crossing 70% of VCC during a STOP
condition, to SDA crossing 70% of VCC during the
following START condition.
1300
ns
tLOW
Clock LOW Time
Measured at the 30% of VCC crossing.
1300
ns
tHIGH
Clock HIGH Time
Measured at the 70% of VCC crossing.
600
ns
tSU:STA
START Condition Setup Time
SCL rising edge to SDA falling edge. Both
crossing 70% of VCC.
600
ns
tHD:STA
START Condition Hold Time
From SDA falling edge crossing 30% of VCC to
SCL falling edge crossing 70% of VCC.
600
ns
tSU:DAT
Input Data Setup Time
From SDA exiting the 30% to 70% of VCC
window, to SCL rising edge crossing 30% of VCC
100
ns
tHD:DAT
Input Data Hold Time
From SCL rising edge crossing 70% of VCC to
SDA entering the 30% to 70% of VCC window.
0ns
tSU:STO
STOP Condition Setup Time
From SCL rising edge crossing 70% of VCC, to
SDA rising edge crossing 30% of VCC.
600
ns
tHD:STO
STOP Condition Hold Time for Read,
or Volatile Only Write
From SDA rising edge to SCL falling edge. Both
crossing 70% of VCC.
600
ns
tHD:STO:NV
STOP Condition Hold Time for Non-
Volatile Write
From SDA rising edge to SCL falling edge. Both
crossing 70% of VCC.
2s
tDH (Note 13)
Output Data Hold Time
From SCL falling edge crossing 30% of VCC, until
SDA enters the 30% to 70% of VCC window.
0ns
tR (Note 13)
SDA and SCL Rise Time
From 30% to 70% of VCC
20 +
0.1 * Cb
250
ns
tF (Note 13)
SDA and SCL Fall Time
From 70% to 30% of VCC
20 +
0.1 * Cb
250
ns
Cb (Note 13)
Capacitive Loading of SDA or SCL
Total on-chip and off-chip
10
400
pF
Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
(Note 1)
MAX
UNITS
ISL95810
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鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
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| ISL95810WIRT8Z | 鍔熻兘鎻忚堪:IC XDCP 256-TAP 10KOHM 8-TDFN RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁�(sh霉)鎿�(j霉)閲囬泦 - 鏁�(sh霉)瀛楅浕浣嶅櫒 绯诲垪:XDCP™ 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 妯�(bi膩o)婧�(zh菙n)鍖呰:2,500 绯诲垪:- 鎺ョ墖:256 闆婚樆锛堟瓙濮嗭級:100k 闆昏矾鏁�(sh霉):2 婧害绯绘暩(sh霉):妯�(bi膩o)婧�(zh菙n)鍊� 35 ppm/°C 瀛樺劜(ch菙)鍣ㄩ鍨�:鏄撳け 鎺ュ彛:6 绶氫覆琛岋紙鑺墖閬告搰锛岄仦澧�锛屽/娓涳級 闆绘簮闆诲:2.6 V ~ 5.5 V 宸ヤ綔婧害:-40°C ~ 125°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:14-TSSOP锛�0.173"锛�4.40mm 瀵級 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:14-TSSOP 鍖呰:甯跺嵎 (TR) |
| ISL95810WIRT8ZR5481 | 鍒堕€犲晢:Intersil Corporation 鍔熻兘鎻忚堪:ISL95810W PRE-PROGRAMMED TO LOWEST RESISTANCE SETTING, XDCP, - Rail/Tube 鍒堕€犲晢:Intersil 鍔熻兘鎻忚堪:ISL95810W PRE-PROGRAMMED TO LOWEST RESISTANCE SETTING, XDCP, |
| ISL95810WIRT8Z-T | 鍔熻兘鎻忚堪:IC XDCP 256-TAP 10KOHM 8-TDFN RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁�(sh霉)鎿�(j霉)閲囬泦 - 鏁�(sh霉)瀛楅浕浣嶅櫒 绯诲垪:XDCP™ 妯�(bi膩o)婧�(zh菙n)鍖呰:3,000 绯诲垪:DPP 鎺ョ墖:32 闆婚樆锛堟瓙濮嗭級:10k 闆昏矾鏁�(sh霉):1 婧害绯绘暩(sh霉):妯�(bi膩o)婧�(zh菙n)鍊� 300 ppm/°C 瀛樺劜(ch菙)鍣ㄩ鍨�:闈炴槗澶� 鎺ュ彛:3 绶氫覆琛岋紙鑺墖閬告搰锛岄仦澧�锛屽/娓涳級 闆绘簮闆诲:2.5 V ~ 6 V 宸ヤ綔婧害:-40°C ~ 85°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:8-WFDFN 瑁搁湶鐒婄洡 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:8-TDFN锛�2x3锛� 鍖呰:甯跺嵎 (TR) |
| ISL95810WIRT8ZTR5481 | 鍒堕€犲晢:Intersil Corporation 鍔熻兘鎻忚堪:ISL95810W PRE-PROGRAMMED TO LOWEST RESISTANCE SETTING, XDCP, - Tape and Reel |
| ISL95810WIU8 | 鍔熻兘鎻忚堪:IC DIGITAL POT 256TP LN LP 8MSOP RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁�(sh霉)鎿�(j霉)閲囬泦 - 鏁�(sh霉)瀛楅浕浣嶅櫒 绯诲垪:XDCP™ 妯�(bi膩o)婧�(zh菙n)鍖呰:2,500 绯诲垪:XDCP™ 鎺ョ墖:256 闆婚樆锛堟瓙濮嗭級:100k 闆昏矾鏁�(sh霉):1 婧害绯绘暩(sh霉):妯�(bi膩o)婧�(zh菙n)鍊� ±300 ppm/°C 瀛樺劜(ch菙)鍣ㄩ鍨�:闈炴槗澶� 鎺ュ彛:I²C锛堣ō(sh猫)鍌欎綅鍧€锛� 闆绘簮闆诲:2.7 V ~ 5.5 V 宸ヤ綔婧害:0°C ~ 70°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:14-TSSOP锛�0.173"锛�4.40mm 瀵級 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:14-TSSOP 鍖呰:甯跺嵎 (TR) |
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