參數(shù)資料
型號(hào): ISL95810UIRT8Z-T
廠商: INTERSIL CORP
元件分類: 數(shù)字電位計(jì)
英文描述: Single Digitally Controlled Potentiometer (XDCP)
中文描述: 50K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 256 POSITIONS, PDSO8
封裝: 3 X 3 MM, ROHS COMPLIANT, PLASTIC, TDFN-8
文件頁(yè)數(shù): 10/13頁(yè)
文件大?。?/td> 1160K
代理商: ISL95810UIRT8Z-T
10
FN8090.1
October 7, 2005
volatile bytes only places the device in its standby mode. A
STOP condition during a write operation to a non-volatile
byte, initiates an internal non-volatile write cycle. The device
enters its standby state when the internal non-volatile write
cycle is completed.
An ACK, Acknowledge, is a software convention used to
indicate a successful data transfer. The transmitting device,
either master or slave, releases the SDA bus after
transmitting eight bits. During the ninth clock cycle, the
receiver pulls the SDA line LOW to acknowledge the
reception of the eight bits of data (See Figure 16).
The ISL95810 responds with an ACK after recognition of a
START condition followed by a valid Identification Byte, and
once again after successful receipt of an Address Byte. The
ISL95810 also responds with an ACK after receiving a Data
Byte of a write operation. The master must respond with an
ACK after receiving a Data Byte of a read operation.
A valid Identification Byte contains 0101000 as the seven
MSBs. The LSB in the Read/Write bit. Its value is “1” for a
Read operation, and “0” for a Write operation (See Table 2).
TABLE 2. IDENTIFICATION BYTE FORMAT
0
1
0
1
0
0
0
R/W
(MSB)
(LSB)
FIGURE 15. VALID DATA CHANGES, START, AND STOP CONDITIONS
FIGURE 16. ACKNOWLEDGE RESPONSE FROM RECEIVER
FIGURE 17. BYTE WRITE SEQUENCE
SDA
SCL
START
DATA
STABLE
DATA
CHANGE
STOP
DATA
STABLE
SDA OUTPUT FROM
TRANSMITTER
SDA OUTPUT FROM
RECEIVER
8
1
9
START
ACK
SCL FROM
MASTER
HIGH IMPEDANCE
HIGH IMPEDANCE
S
T
A
R
T
S
T
O
P
IDENTIFICATION
BYTE
ADDRESS
BYTE
DATA
BYTE
A
C
K
SIGNALS FROM
THE MASTER
SIGNALS FROM
THE ISL95810
A
C
K
0
0
0
1
1
A
C
K
WRITE
SIGNAL AT SDA
0 0 0 0
0
0
0
0 0 0
ISL95810
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