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參數(shù)資料
| 型號： | ISL95711 |
| 廠商： | Intersil Corporation |
| 英文描述： | Terminal Voltage 3V or 5V, 128 Taps I2C Serial Interface |
| 中文描述： | 終端電壓3V或5V，128絲錐I2C串行接口 |
| 文件頁數(shù)： | 8/12頁 |
| 文件大小： | 333K |
| 代理商： | ISL95711 |
8
FN8241.2
August 15, 2005
between R
L
and R
H
. Soon after the power supply voltage
becomes large enough for reliable non-volatile memory
reading (~ ± 2.5V), the ISL95711 reads the value stored on a
non-volatile Initial Value Register (IVR) and loads it into the
WR.
The WR and IVR can be read or written directly using the
I
2
C serial interface as described in the following sections.
Memory Description
The ISL95711 contains 1 non-volatile byte know as the Initial
Value Register (IVR). It is accessed by the I
2
C interface
operations with Address 00h. The IVR contains the value
which is loaded into the Volatile Wiper Register (WR) at
power-up.
The volatile WR, and the non-volatile IVR of a DCP are
accessed with the same address.
The Access Control Register (ACR) determines which byte
at address 00h is accessed (IVR or WR). The volatile ACR
must be set as follows:
When the ACR is all zeroes, which is the default at power-
up:
A read operation to address 0 outputs the value of the
non-volatile IVR.
A write operation to address 0 writes the same value to
the WR and IVR of the corresponding DCP.
When the ACR is 80h:
A read operation to address 0 outputs the value of the
volatile WR.
A write operation to address 0 only writes to the
corresponding volatile WR.
It is not possible to write to an IVR without writing the same
value to its corresponding WR.
00h and 80h are the only values that should be written to
address 2. All other values are reserved and must not be
written to address 2.
The ISL95711 is pre-programmed with 40h in the IVR.
I
2
C Serial Interface
The ISL95711 supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data onto the
bus as a transmitter and the receiving device as the receiver.
The device controlling the transfer is a master and the
device being controlled is the slave. The master always
initiates data transfers and provides the clock for both
transmit and receive operations. Therefore, the ISL95711
operates as a slave device in all applications.
All communication over the I
2
C interface is conducted by
sending the MSB of each byte of data first.
Protocol Conventions
Data states on the SDA line can change only during SCL
LOW periods. SDA state changes during SCL HIGH are
reserved for indicating START and STOP conditions (See
Figure 1). On power-up of the ISL95711 the SDA pin is in the
input mode.
All I
2
C interface operations must begin with a START
condition, which is a HIGH to LOW transition of SDA while
SCL is HIGH. The ISL95711 continuously monitors the SDA
and SCL lines for the START condition and does not
respond to any command until this condition is met (See
Figure 1). A START condition is ignored during the power-up
sequence and during internal non-volatile write cycles.
All I
2
C interface operations must be terminated by a STOP
condition, which is a LOW to HIGH transition of SDA while
SCL is HIGH (See Figure 1). A STOP condition at the end of
a read operation, or at the end of a write operation to volatile
bytes only places the device in its standby mode. A STOP
condition during a write operation to a non-volatile byte,
initiates an internal non-volatile write cycle. The device
enters its standby state when the internal non-volatile write
cycle is completed.
An ACK, Acknowledge, is a software convention used to
indicate a successful data transfer. The transmitting device,
either master or slave, releases the SDA bus after
transmitting eight bits. During the ninth clock cycle, the
receiver pulls the SDA line LOW to acknowledge the
reception of the eight bits of data (See Figure 2).
The ISL95711 responds with an ACK after recognition of a
START condition followed by a valid Identification Byte, and
once again after successful receipt of an Address Byte. The
ISL95711 also responds with an ACK after receiving a Data
Byte of a write operation. The master must respond with an
ACK after receiving a Data Byte of a read operation
A valid Identification Byte contains 01010 as the five MSBs,
and the following two bits matching the logic values present
at pins A1, and A0. The LSB is in the Read/Write bit. Its
value is “1” for a Read operation, and “0” for a Write
operation. (See Table 2.)
TABLE 2. IDENTIFICATION BYTE FORMAT
Logic values at pins A1, and A0 respectively
TABLE 1. MEMORY MAP
ADDRESS
NON-VOLATILE
VOLATILE
2
-
ACR
1
Reserved
0
IVR
WR
WR: Wiper Register, IVR: Initial value Register.
0
1
0
1
0
A1
A0
R/W
(MSB)
(LSB)
ISL95711
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