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參數(shù)資料
| 型號： | ISL9216IRZ |
| 廠商： | INTERSIL CORP |
| 元件分類： | 電源管理 |
| 英文描述： | 8 to 12 Cell Li-Ion Battery Overcurrent Protection and Analog Front End Chip Set |
| 中文描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PQCC32 |
| 封裝： | 5 X 5 MM, ROHS COMPLIANT, PLASTIC, MO-220VHHD-2, QFN-32 |
| 文件頁數(shù)： | 28/33頁 |
| 文件大小： | 645K |
| 代理商： | ISL9216IRZ |
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28
FN6488.1
November 2, 2007
When data is clocked into the ISL9216 through the I
2
C port, it
is immediately transferred to the serial cascade port, so both
the ISL9216 and ISL9217 see the slave byte at the same
time. After the 8th slave bit, the device that receives the
correct slave byte sends an acknowledge, while the other
device ignores all subsequent data on the serial port until it
receives a stop bit. However, even though the ISL9216
ignores the data, it still passes it through to the ISL9217.
The SDAI and SDAO pins of the ISL9217 need to have pull-
up resistors of approximately 4.7k
Ω
, since the output drivers
are open-drain devices.
Register Protection
The Discharge Set, Charge Set, and Feature Set
configuration registers are write protected on initial power-
up. In order to write to these registers it is necessary to set a
bit to enable each one. These write enable bits are in the
Write Enable register (Address 08H).
Write the FSETEN bit (Addr 8:bit 7) to “1” to change the data
in the Feature Set register (Address 7).
Write the CHSETEN bit (Addr 8:bit 6) to “1” to change the
data in the Feature Set register (Address 6).
Write the DISSETEN bit (Addr 8:bit 5) to “1” to change the
data in the Feature Set register (Address 5).
The microcontroller can reset these bits back to zero to
prevent inadvertent writes that change the operation of the
pack.
Operation State Machine
Figure 16 shows a device state machine which defines how
the ISL9216 and ISL9217 respond to various conditions.
Power Fails and one of the supplies, V
CC
, V
CELL1
, V
CELL2
,
and V
CELL3
do not meet minimum voltage requirements
WKUP goes above or below
threshold (edge triggered).
[ISL9217 wake-up requires μC
command to ISL9216].
Or, SLEEP bit is set to ‘0’
I
2
C interface is disabled. Biasing is disabled.
All registers set to default values (All “0”)
POWER-DOWN STATE
I
2
C interface is enabled. Biasing is enabled.
Voltage Regulator is enabled.
POWER-UP STATE
Voltage Regulator is ON
Logic and registers are powered by RGO
CFET, DFET, Cell balancing outputs are all off.
(Require external command to turn on)
Charge and discharge current protection
circuits and temperature protection circuits are
active (Default). Overcurrent conditions force
power FETs to turn off. Over-temperature
conditions force power FETs and cell balance
outputs to turn off.
Voltage and temperature monitoring circuits
are awaiting external control.
MAIN OPERATING STATE
Power is applied and all of the supplies, V
CC
, V
CELL1
,
V
CELL2
, and V
CELL3
meet minimum voltage requirements
Voltage Regulator is OFF
Biasing is OFF
Logic and registers are powered by V
CELL1
CFET, DFET, Cell balancing outputs are all off.
Charge and discharge current protection
circuits all off.
Voltage and temperature monitoring circuits
are off.
I
2
C communication is active (if V
CELL1
voltage
is high enough to operate with external
device.)
SLEEP STATE
SLEEP bit is set to ‘1’
FIGURE 16. DEVICE OPERATION STATE MACHINE
ISL9216, ISL9217
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