參數(shù)資料
型號: ISL9208
廠商: Intersil Corporation
英文描述: Multi-Cell Li-ion Battery Pack OCP/Analog Front End(多節(jié)鋰離子電池組OCP/模擬前端)
中文描述: 多單元鋰離子電池OCP /模擬前端(多節(jié)鋰離子電池組OCP /模擬前端)
文件頁數(shù): 15/28頁
文件大?。?/td> 504K
代理商: ISL9208
15
FN6446.1
November 2, 2007
Configuration Registers
The device is configured for specific application
requirements using the Configuration Registers. The
configuration registers consist of SRAM memory.
This memory is powered by the RGO output. In a sleep
condition, an internal switch converts power for the contents
of these registers from RGO to the VCELL1 input.
TABLE 6. FET CONTROL REGISTER (ADDR: 04H)
BIT
FUNCTION
DESCRIPTION
7
SLEEP
Force Sleep
Setting this bit to “1” forces the device to go into a sleep condition. This turns off both FET
outputs, the cell balance outputs and the voltage regulator. This also resets the CFET, DFET,
and CB7ON:CB1ON bits. The SLEEP bit is automatically reset to “0” when the device wakes
up. This bit does not reset the AO3:AO0 bits.
6
LDMONEN
Turn on VMON connection
Writing a “1” to this bit turns on the VMON circuit. Writing a “0” to this bit turns off the VMON
circuit. As such, the microcontroller has full control of the operation of this circuit.
5:2
RESERVED
Reserved for future expansion.
1
CFET
Setting this bit to “1” turns on the charge FET.
Setting this bit to “0” turns off the charge FET.
This bit is automatically reset in the event of a charge overcurrent condition, unless the
automatic response is disabled by the DENOCC bit.
0
DFET
Setting this bit to “1” turns on the discharge FET.
Setting this bit to “0” turns off the discharge FET.
This bit is automatically reset in the event of a discharge overcurrent or discharge short circuit
condition, unless the automatic response is disabled by the DENOCD or DENSCD bits.
TABLE 7. DISCHARGE SET CONFIG REGISTER (ADDR: 05H)
SETTING
FUNCTION
Bit 7
DENOCD
Turn off automatic OC
discharge control
When set to ‘0’, a discharge overcurrent condition automatically turns off the FETs.
When set to ‘1’, a discharge overcurrent condition will not automatically turn off the FETs.
In either case, this condition sets the DOC bit, which also turns on the TEMP3V output.
BIT 6
OCDV1
BIT 5
OCDV0
OVERCURRENT DISCHARGE VOLTAGE THRESHOLD
0
0
V
OCD
= 0.10V
V
OCD
= 0.12V
V
OCD
= 0.14V
V
OCD
= 0.16V
When set to ‘0’, a discharge short circuit condition turns off the FETs.
When set to ‘1’, a discharge short circuit condition will not automatically turn off the FETs.
In either case, the condition sets the SCD bit, which also turns on the TEMP3V output.
0
1
1
0
1
1
Bit 4
DENSCD
Turn off automatic SC
discharge control
BIT 3
SCDV1
BIT 2
SCDV0
SHORT CIRCUIT DISCHARGE VOLTAGE THRESHOLD
0
0
V
SCD
= 0.20V
V
SCD
= 0.35V
V
SCD
= 0.65V
V
SCD
= 1.20V
0
1
1
0
1
1
BIT 1
OCDT1
BIT 0
OCDT0
OVERCURRENT DISCHARGE TIME-OUT
0
0
t
OCD
= 160ms (2.5ms if DTDIV = 1)
t
OCD
= 320ms (5ms if DTDIV = 1)
t
OCD
= 640ms (10ms if DTDIV = 1)
t
OCD
= 1280ms (20ms if DTDIV = 1)
0
1
1
0
1
1
ISL9208
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