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參數(shù)資料
| 型號： | ISL90842UIV1427Z |
| 廠商： | INTERSIL CORP |
| 元件分類： | 數(shù)字電位計 |
| 英文描述： | Quad Digitally Controlled Variable Resistors |
| 中文描述： | QUAD 50K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 256 POSITIONS, PDSO14 |
| 封裝： | ROHS COMPLIANT, PLASTIC, TSSOP-14 |
| 文件頁數(shù)： | 7/10頁 |
| 文件大小： | 678K |
| 代理商： | ISL90842UIV1427Z |
7
FN8096.1
January 16, 2006
Principles of Operation
The ISL90842 is an integrated circuit incorporating four
DCPs with their associated registers, and an I
2
C serial
interface providing direct communication between a host
and the DCPs.
DCP Description
Each DCP is implemented with a combination of resistor
elements and CMOS switches. The physical ends of each
DCP are equivalent to the fixed terminals of a mechanical
potentiometer. The R
W
pin of each DCP is connected to
intermediate nodes, and is equivalent to the wiper terminal
of a mechanical potentiometer. The position of the wiper
terminal within the DCP is controlled by an 8-bit volatile
Wiper Register (WR). Each DCP has its own WR. When the
WR of a DCP contains all zeroes (WR<7:0>: 00h), its wiper
terminal (R
W
) is closest to its R
L
terminal. When the WR of a
DCP contains all ones (WR<7:0>: FFh), its wiper terminal
(R
W
) is furthest from the R
H
terminal. As the value of the
WR increases from all zeroes (00h) to all ones (255
decimal), the wiper moves monotonically from the position
furthest from R
H
to a position closer to R
H
. At the same time,
the resistance between R
H
and R
W
decreases
monotonically. Note that the R
L
terminals for all four pots are
not connected (left floating).
While the ISL90842 is being powered up, all four WRs are
reset to 80h (128 decimal), which locates R
W
roughly at a
position which yields a rheostat setting that is about 1/2 of
R
TOTAL
.
The WRs can be read or written directly using the I
2
C serial
interface as described in the following sections. The I
2
C
interface Address Byte has to be set to 00h, 01h, 02h, and
03h to access the WR of DCP0, DCP1, DCP2, and DCP3,
respectively.
I
2
C Serial Interface
The ISL90842 supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data onto the
bus as a transmitter and the receiving device as the receiver.
The device controlling the transfer is a master and the
device being controlled is the slave. The master always
initiates data transfers and provides the clock for both
transmit and receive operations. Therefore, the ISL90842
operates as a slave device in all applications.
All communication over the I
2
C interface is conducted by
sending the MSB of each byte of data first.
Protocol Conventions
Data states on the SDA line must change only during SCL
LOW periods. SDA state changes during SCL HIGH are
reserved for indicating START and STOP conditions (See
Figure 9). On power-up of the ISL90842 the SDA pin is in the
input mode.
All I
2
C interface operations must begin with a START
condition, which is a HIGH to LOW transition of SDA while
SCL is HIGH. The ISL90842 continuously monitors the SDA
and SCL lines for the START condition and does not
respond to any command until this condition is met (See
Figure 9). A START condition is ignored during the power-up
of the device.
All I
2
C interface operations must be terminated by a STOP
condition, which is a LOW to HIGH transition of SDA while
SCL is HIGH (See Figure 9). A STOP condition at the end of
a read operation, or at the end of a write operation places
the device in its standby mode.
An ACK, Acknowledge, is a software convention used to
indicate a successful data transfer. The transmitting device,
either master or slave, releases the SDA bus after
transmitting eight bits. During the ninth clock cycle, the
receiver pulls the SDA line LOW to acknowledge the
reception of the eight bits of data (See Figure 10).
FIGURE 7. FREQUENCY RESPONSE (2.2MHz)
FIGURE 8. LARGE SIGNAL SETTLING TIME
Typical Performance Curves
(Continued)
TAP POSITION = MID POINT
R
TOTAL
=9.4K
OUTPUT
INPUT
SCL
SIGNAL AT WIPER
(WIPER UNLOADED
MOVEMENT FROM
ffh TO 00h)
ISL90842
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ISL90842WIV1427Z | Quad Digitally Controlled Variable Resistors |
| ISL90843UIU1027Z | Quad Digital Controlled Potentiometers (XDCP⑩) |
| ISL90843WIU1027Z | Quad Digital Controlled Potentiometers (XDCP⑩) |
| ISL90843 | Low Noise, Low Power, I2C Bus, 256 Taps(低噪聲, 低功率, I2C總線, 256抽頭數(shù)字電位器) |
| ISL9208 | Multi-Cell Li-ion Battery Pack OCP/Analog Front End(多節(jié)鋰離子電池組OCP/模擬前端) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISL90842UIV1427Z-TK | 功能描述:IC POT DGTL QUAD 50K OHM 14TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)字電位器 系列:XDCP™ 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 接片:256 電阻（歐姆）:100k 電路數(shù):1 溫度系數(shù):標準值 35 ppm/°C 存儲器類型:非易失 接口:3 線串口 電源電壓:2.7 V ~ 5.25 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-WDFN 裸露焊盤 供應(yīng)商設(shè)備封裝:8-TDFN-EP（3x3） 包裝:剪切帶 (CT) 產(chǎn)品目錄頁面:1399 (CN2011-ZH PDF) 其它名稱:MAX5423ETA+TCT |
| ISL90842WIV1427 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Low Noise, Low Power, I2C Bus, 256 Taps |
| ISL90842WIV1427Z | 功能描述:IC DCP 256-TAP 10KOHM TSSOP-14 RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)字電位器 系列:XDCP™ 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 接片:256 電阻（歐姆）:100k 電路數(shù):2 溫度系數(shù):標準值 35 ppm/°C 存儲器類型:易失 接口:6 線串行（芯片選擇，遞增，增/減） 電源電壓:2.6 V ~ 5.5 V 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:14-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:14-TSSOP 包裝:帶卷 (TR) |
| ISL90842WIV1427Z-TK | 功能描述:IC POT DGTL QUAD 10K OHM 14TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)字電位器 系列:XDCP™ 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 接片:256 電阻（歐姆）:100k 電路數(shù):1 溫度系數(shù):標準值 35 ppm/°C 存儲器類型:非易失 接口:3 線串口 電源電壓:2.7 V ~ 5.25 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-WDFN 裸露焊盤 供應(yīng)商設(shè)備封裝:8-TDFN-EP（3x3） 包裝:剪切帶 (CT) 產(chǎn)品目錄頁面:1399 (CN2011-ZH PDF) 其它名稱:MAX5423ETA+TCT |
| ISL90843 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Quad Digital Controlled Potentiometers (XDCP⑩) |
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