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參數(shù)資料
| 型號： | ISL90840 |
| 廠商： | Intersil Corporation |
| 英文描述： | Low Noise, Low Power I2C Bus, 256 Taps |
| 中文描述： | 低噪聲，低功耗I2C總線，256絲錐 |
| 文件頁數(shù)： | 4/12頁 |
| 文件大?。?/td> | 1127K |
| 代理商： | ISL90840 |
4
FN8086.0
July 27, 2005
Operating Specifications
Over the recommended operating conditions unless otherwise specified.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
(NOTE 1)
MAX
UNIT
I
CC1
V
CC
supply current (volatile
write/read)
f
SCL
= 400kHz; SDA = Open; (for I
2
C, active,
read and write states)
1
mA
I
SB
V
CC
current (standby)
V
CC
= +5.5V, I
2
C interface in standby state
V
CC
= +3.6V, I
2
C interface in standby state
5
μA
2
μA
I
LkgDig
Leakage current, at pins A0, A1, A2,
SDA, and SCL
Voltage at pin from GND to V
CC
-10
10
μA
t
DCP
(Note 15)
DCP wiper response time
SCL falling edge of last bit of DCP data byte
to wiper change
1
μs
SERIAL INTERFACE SPECS
V
IL
A2, A1, A0, SDA, and SCL input buffer
LOW voltage
-0.3
0.3*V
CC
V
V
IH
A2, A1, A0, SDA, and SCL input buffer
HIGH voltage
0.7*V
CC
V
CC
+0.3
V
Hysteresis
(Note 15)
SDA and SCL input buffer hysteresis
0.05*
V
CC
V
V
OL
(Note 15)
SDA output buffer LOW voltage,
sinking 4mA
0
0.4
V
Cpin
(Note 15)
A2, A1, A0, SDA, and SCL pin
capacitance
10
pF
f
SCL
t
IN
SCL frequency
400
kHz
(Note 15)
Pulse width suppression time at SDA
and SCL inputs
Any pulse narrower than the max spec is
suppressed
50
ns
t
AA
(Note 15)
SCL falling edge to SDA output data
valid
SCL falling edge crossing 30% of V
CC
, until
SDA exits the 30% to 70% of V
CC
window
900
ns
t
BUF
(Note 15)
Time the bus must be free before the
start of a new transmission
SDA crossing 70% of V
CC
during a STOP
condition, to SDA crossing 70% of V
CC
during the following START condition
1300
ns
t
LOW
Clock LOW time
Measured at the 30% of V
CC
crossing
1300
ns
t
HIGH
Clock HIGH time
Measured at the 70% of V
CC
crossing
600
ns
t
SU:STA
START condition setup time
SCL rising edge to SDA falling edge; both
crossing 70% of V
CC
600
ns
t
HD:STA
START condition hold time
From SDA falling edge crossing 30% of V
CC
to SCL falling edge crossing 70% of V
CC
600
ns
t
SU:DAT
Input data setup time
From SDA exiting the 30% to 70% of V
CC
window, to SCL rising edge crossing 30% of
V
CC
100
ns
t
HD:DAT
Input data hold time
From SCL rising edge crossing 70% of V
CC
to SDA entering the 30% to 70% of V
CC
window
0
ns
t
SU:STO
STOP condition setup time
From SCL rising edge crossing 70% of V
CC
,
to SDA rising edge crossing 30% of V
CC
600
ns
t
HD:STO
STOP condition hod time for read, or
volatile only write
From SDA rising edge to SCL falling edge;
both crossing 70% of V
CC
600
ns
t
DH
(Note 15)
Output data hold time
From SCL falling edge crossing 30% of V
CC
,
until SDA enters the 30% to 70% of V
CC
window
0
ns
t
R
(Note 15)
SDA and SCL rise time
From 30% to 70% of V
CC
20 +
0.1 * Cb
250
ns
ISL90840
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