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參數(shù)資料
| 型號： | ISL90810WIU8Z |
| 廠商： | INTERSIL CORP |
| 元件分類： | 數(shù)字電位計(jì) |
| 英文描述： | Low Noise/Low Power/I2C Bus/256 Taps |
| 中文描述： | 10K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 256 POSITIONS, PDSO8 |
| 封裝： | ROHS COMPLIANT, PLASTIC, MO-187AA, MSOP-8 |
| 文件頁數(shù)： | 4/11頁 |
| 文件大小： | 1126K |
| 代理商： | ISL90810WIU8Z |
4
FN8234.1
October 13, 2005
t
DCP
(Note 13) DCP Wiper Response Time
SCL falling edge of last bit of DCP Data Byte to
wiper change
1
μs
Vpor
Power-On Recall Voltage
Minimum V
CC
at which memory recall occurs
1.8
2.6
V
V
CC
Ramp
t
D
(Note 13)
V
CC
Ramp Rate
0.2
V/ms
Power-Up Delay
V
CC
above Vpor, to DCP Initial Value Register
recall completed, and I
2
C Interface in standby state
3
ms
SERIAL INTERFACE SPECIFICATIONS
V
IL
SDA, and SCL Input Buffer LOW
Voltage
-0.3
0.3*V
CC
V
V
IH
SDA, and SCL Input Buffer HIGH
Voltage
0.7*V
CC
V
CC
+0.3
V
Hysteresis
(Note 13)
V
OL
(Note 13)
SDA and SCL Input Buffer Hysteresis
0.05*
V
CC
V
SDA Output Buffer LOW Voltage,
Sinking 4mA
Cpin
(Note 13) SDA, and SCL Pin Capacitance
0
0.4
V
10
pF
f
SCL
SCL Frequency
400
kHz
t
IN
(Note 13)
Pulse Width Suppression Time at
SDA and SCL Inputs
Any pulse narrower than the max spec is
suppressed.
50
ns
t
AA
(Note 13)
SCL Falling Edge to SDA Output Data
Valid
t
BUF
(Note 13) Time the Bus Must be Free Before the
Start of a New Transmission
SCL falling edge crossing 30% of V
CC
, until SDA
exits the 30% to 70% of V
CC
window.
900
ns
SDA crossing 70% of V
CC
during a STOP
condition, to SDA crossing 70% of V
CC
during
the following START condition.
1300
ns
t
LOW
Clock LOW Time
Measured at the 30% of V
CC
crossing.
1300
ns
t
HIGH
Clock HIGH Time
Measured at the 70% of V
CC
crossing.
600
ns
t
SU:STA
START Condition Setup Time
SCL rising edge to SDA falling edge. Both
crossing 70% of V
CC
.
600
ns
t
HD:STA
START Condition Hold Time
From SDA falling edge crossing 30% of V
CC
to
SCL falling edge crossing 70% of V
CC
.
600
ns
t
SU:DAT
Input Data Setup Time
From SDA exiting the 30% to 70% of V
CC
window, to SCL rising edge crossing 30% of V
CC
100
ns
t
HD:DAT
Input Data Hold Time
From SCL rising edge crossing 70% of V
CC
to
SDA entering the 30% to 70% of V
CC
window.
0
ns
t
SU:STO
STOP Condition Setup Time
From SCL rising edge crossing 70% of V
CC
, to
SDA rising edge crossing 30% of V
CC
.
600
ns
t
HD:STO
STOP Condition Hold Time for Read,
or Volatile Only Write
From SDA rising edge to SCL falling edge. Both
crossing 70% of V
CC
.
600
ns
t
DH
(Note 13)
Output Data Hold Time
From SCL falling edge crossing 30% of V
CC
, until
SDA enters the 30% to 70% of V
CC
window.
0
ns
t
R
(Note 13)
SDA and SCL Rise Time
From 30% to 70% of V
CC
20 +
0.1 * Cb
250
ns
t
F
(Note 13)
SDA and SCL Fall Time
From 70% to 30% of V
CC
20 +
0.1 * Cb
250
ns
Cb
(Note 13)
Rpu
(Note 13)
Capacitive Loading of SDA or SCL
Total on-chip and off-chip
10
400
pF
SDA and SCL Bus Pull-Up Resistor
Off-Chip
Maximum is determined by t
R
and t
F
.
For Cb = 400pF, max is about 2~2.5k
.
For Cb = 40pF, max is about 15~20k
1
k
Operating Specifications
Over the recommended operating conditions unless otherwise specified.
(Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
(Note 1)
MAX
UNITS
ISL90810
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