參數(shù)資料
型號： ISL90810UAU8Z
廠商： INTERSIL CORP
元件分類： 數(shù)字電位計
英文描述： Single Digitally Controlled Potentiometer
中文描述： 50K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 256 POSITIONS, PDSO8
封裝： ROHS COMPLIANT, PLASTIC, MO-187AA, MSOP-8
文件頁數(shù)： 4/11頁
文件大?。?/td> 1093K
代理商： ISL90810UAU8Z
4
FN8234.2
November 10, 2006
Operating Specifications
Over the recommended operating conditions unless otherwise specified.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
(Note 1)
MAX
UNITS
I
CC1
V
CC
Supply Current
(Volatile Write/Read)
f
SCL
= 400kHz; SDA = Open; (for I
2
C, Active,
Read and Volatile Write States only)
V
CC
= +5.5V, I
2
C Interface in Standby State,
Temperature range from -40°C to +85°C
V
CC
= +5.5V, I
2
C Interface in Standby State,
Temperature range from -40°C to +105°C
V
CC
= +3.6V, I
2
C Interface in Standby State,
Temperature range from -40°C to +85°C
V
CC
= +3.6V, I
2
C Interface in Standby State,
Temperature range from -40°C to +105°C
20
100
μA
I
SB
V
CC
Current (Standby)
2
5
μA
2
8
μA
0.8
2
μA
0.8
5
μA
I
LkgDig
Leakage Current at Pins SDA and
SCL
t
DCP
(Note 14) DCP Wiper Response Time
Voltage at pin from GND to V
CC
-10
10
μA
SCL falling edge of last bit of DCP Data Byte to
wiper change
1
μs
Vpor
Power-On Recall Voltage
Minimum V
CC
at which memory recall occurs
1.8
2.6
V
V
CC
Ramp
t
D
(Note 14)
V
CC
Ramp Rate
Power-Up Delay
0.2
V/ms
V
CC
above Vpor, to DCP Initial Value Register
recall completed, and I
2
C Interface in standby state
3
ms
SERIAL INTERFACE SPECIFICATIONS
V
IL
SDA, and SCL Input Buffer LOW
Voltage
-0.3
0.3*V
CC
V
V
IH
SDA, and SCL Input Buffer HIGH
Voltage
0.7*V
CC
V
CC
+0.3
V
Hysteresis
(Note 14)
V
OL
(Note 14)
SDA and SCL Input Buffer Hysteresis
0.05*
V
CC
0
V
SDA Output Buffer LOW Voltage,
Sinking 4mA
Cpin
(Note 14) SDA, and SCL Pin Capacitance
0.4
V
10
pF
f
SCL
SCL Frequency
400
kHz
t
IN
(Note 14)
Pulse Width Suppression Time at
SDA and SCL Inputs
Any pulse narrower than the max spec is
suppressed.
50
ns
t
AA
(Note 14)
SCL Falling Edge to SDA Output Data
Valid
t
BUF
(Note 14) Time the Bus Must be Free Before the
Start of a New Transmission
SCL falling edge crossing 30% of V
CC
, until SDA
exits the 30% to 70% of V
CC
window.
SDA crossing 70% of V
CC
during a STOP
condition, to SDA crossing 70% of V
CC
during
the following START condition.
900
ns
1300
ns
t
LOW
t
HIGH
t
SU:STA
Clock LOW Time
Measured at the 30% of V
CC
crossing.
Measured at the 70% of V
CC
crossing.
SCL rising edge to SDA falling edge. Both
crossing 70% of V
CC
.
From SDA falling edge crossing 30% of V
CC
to
SCL falling edge crossing 70% of V
CC
.
From SDA exiting the 30% to 70% of V
CC
window, to SCL rising edge crossing 30% of V
CC
From SCL rising edge crossing 70% of V
CC
to
SDA entering the 30% to 70% of V
CC
window.
From SCL rising edge crossing 70% of V
CC
, to
SDA rising edge crossing 30% of V
CC
.
1300
ns
Clock HIGH Time
600
ns
START Condition Setup Time
600
ns
t
HD:STA
START Condition Hold Time
600
ns
t
SU:DAT
Input Data Setup Time
100
ns
t
HD:DAT
Input Data Hold Time
0
ns
t
SU:STO
STOP Condition Setup Time
600
ns
ISL90810
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