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參數(shù)資料
| 型號： | ISL90728 |
| 廠商： | Intersil Corporation |
| 元件分類： | 數(shù)字電位計 |
| 英文描述： | Digitally Controlled Potentiometer(數(shù)控電位器) |
| 中文描述： | 數(shù)控電位器（數(shù)控電位器） |
| 文件頁數(shù)： | 4/8頁 |
| 文件大?。?/td> | 170K |
| 代理商： | ISL90728 |
4
FN8247.4
August 2, 2006
Operating Specifications
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
(Note 3)
MAX
UNIT
I
CC1
V
CC
Supply Current
(Volatile write/read)
f
SCL
= 400kHz; SDA = Open; (for I
2
C, Active,
Read and Volatile Write States only)
200
μA
I
SB
V
CC
Current (standby)
V
CC
= +5.5V, I
2
C Interface in Standby State
500
nA
I
ComLkg
t
DCP
(Note 12) DCP Wiper Response Time
Common-Mode Leakage
Voltage at SDA pin to GND or V
CC
3
μA
SCL falling edge of last bit of DCP Data Byte to
wiper change
500
ns
V
CC
Ramp
V
CC
Ramp Rate
0.2
V/ms
t
D
Power-up Delay
V
CC
above Vpor, to DCP Initial Value Register
recall completed, and I
2
C Interface in standby state
3
ms
SERIAL INTERFACE SPECIFICATIONS
V
IL
SDA, and SCL Input Buffer LOW
Voltage
-0.3
0.3*
V
CC
V
V
IH
SDA, and SCL Input Buffer HIGH
Voltage
0.7*
V
CC
V
CC
+
0.3
V
Hysteresis
SDA and SCL Input Buffer Hysteresis
0.05*
V
CC
V
V
OL
SDA Output Buffer LOW Voltage,
Sinking 4mA
0
0.4
V
Cpin
(Note 14) SDA, and SCL Pin Capacitance
10
pF
f
SCL
SCL Frequency
400
kHz
t
IN
Pulse Width Suppression Time at
SDA and SCL Inputs
Any pulse narrower than the max spec is
suppressed.
50
ns
t
AA
SCL Falling Edge to SDA Output Data
Valid
SCL falling edge crossing 30% of V
CC
, until SDA
exits the 30% to 70% of V
CC
window.
900
ns
t
BUF
Time the Bus Must be Free Before the
Start of a New Transmission
SDA crossing 70% of V
CC
during a STOP
condition, to SDA crossing 70% of V
CC
during
the following START condition.
1300
ns
t
LOW
Clock LOW Time
Measured at the 30% of V
CC
crossing.
1300
ns
t
HIGH
Clock HIGH Time
Measured at the 70% of V
CC
crossing.
600
ns
t
SU:STA
START Condition Setup Time
SCL rising edge to SDA falling edge. Both
crossing 70% of V
CC
.
600
ns
t
HD:STA
START Condition Hold Time
From SDA falling edge crossing 30% of V
CC
to
SCL falling edge crossing 70% of V
CC
.
600
ns
t
SU:DAT
Input Data Setup Time
From SDA exiting the 30% to 70% of V
CC
window, to SCL rising edge crossing 30% of V
CC
100
ns
t
HD:DAT
Input Data Hold Time
From SCL rising edge crossing 70% of V
CC
to
SDA entering the 30% to 70% of V
CC
window.
0
ns
t
SU:STO
STOP Condition Setup Time
From SCL rising edge crossing 70% of V
CC
, to
SDA rising edge crossing 30% of V
CC
.
600
ns
t
HD:STO
STOP Condition Hold Time for Read,
or Volatile Only Write
From SDA rising edge to SCL falling edge. Both
crossing 70% of V
CC
.
600
ns
t
DH
Output Data Hold Time
From SCL falling edge crossing 30% of V
CC
,
until SDA enters the 30% to 70% of V
CC
window.
0
ns
t
R
(Note 14)
SDA and SCL Rise Time
From 30% to 70% of V
CC
20 +
0.1 * Cb
250
ns
ISL90727, ISL90728
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