參數(shù)資料
型號(hào)： ISL90727WIE6Z-TK
廠商： INTERSIL CORP
元件分類： 數(shù)字電位計(jì)
英文描述： Digitally Controlled Potentiometer (XDCP)
中文描述： 10K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 128 POSITIONS, PDSO6
封裝： LEAD FREE, MO-203-AB, SC-70, 6 PIN
文件頁(yè)數(shù)： 4/8頁(yè)
文件大?。?/td> 227K
代理商： ISL90727WIE6Z-TK
4
FN8247.1
August 1, 2005
Operating Specifications
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
(Note 1)
MAX
UNIT
I
CC1
V
CC
supply current
(Volatile write/read)
f
SCL
= 400kHz; SDA = Open; (for I
2
C, Active,
Read and Volatile Write States only)
200
μA
I
SB
V
CC
current (standby)
V
CC
= +5.5V, I
2
C Interface in Standby State
500
nA
I
ComLkg
t
DCP
(Note 10)
Common-Mode Leakage
Voltage at SDA pin to GND or V
CC
3
μA
DCP wiper response time
SCL falling edge of last bit of DCP Data Byte to
wiper change
500
ns
V
CC
Ramp
V
CC
ramp rate
0.2
V/ms
t
D
Power-up delay
V
CC
above Vpor, to DCP Initial Value Register
recall completed, and I
2
C Interface in standby
state
3
ms
SERIAL INTERFACE SPECIFICATIONS
V
IL
SDA, and SCL input buffer LOW
voltage
-0.3
0.3*
V
CC
V
V
IH
SDA, and SCL input buffer HIGH
voltage
0.7*
V
CC
V
CC
+
0.3
V
Hysteresis
SDA and SCL input buffer
hysteresis
0.05*
V
CC
V
V
OL
SDA output buffer LOW voltage,
sinking 4mA
0
0.4
V
Cpin
(Note 12)
SDA, and SCL pin capacitance
10
pF
f
SCL
SCL frequency
400
kHz
t
IN
Pulse width suppression time at
SDA and SCL inputs
Any pulse narrower than the max spec is
suppressed.
50
ns
t
AA
SCL falling edge to SDA output
data valid
SCL falling edge crossing 30% of V
CC
, until SDA
exits the 30% to 70% of V
CC
window.
900
ns
t
BUF
Time the bus must be free before
the start of a new transmission
SDA crossing 70% of V
CC
during a STOP
condition, to SDA crossing 70% of V
CC
during
the following START condition.
1300
ns
t
LOW
Clock LOW time
Measured at the 30% of V
CC
crossing.
1300
ns
t
HIGH
Clock HIGH time
Measured at the 70% of V
CC
crossing.
600
ns
t
SU:STA
START condition setup time
SCL rising edge to SDA falling edge. Both
crossing 70% of V
CC
.
600
ns
t
HD:STA
START condition hold time
From SDA falling edge crossing 30% of V
CC
to
SCL falling edge crossing 70% of V
CC
.
600
ns
t
SU:DAT
Input data setup time
From SDA exiting the 30% to 70% of V
CC
window, to SCL rising edge crossing 30% of V
CC
100
ns
t
HD:DAT
Input data hold time
From SCL rising edge crossing 70% of V
CC
to
SDA entering the 30% to 70% of V
CC
window.
0
ns
t
SU:STO
STOP condition setup time
From SCL rising edge crossing 70% of V
CC
, to
SDA rising edge crossing 30% of V
CC
.
600
ns
t
HD:STO
STOP condition hold time for
read, or volatile only write
From SDA rising edge to SCL falling edge. Both
crossing 70% of V
CC
.
600
ns
t
DH
Output data hold time
From SCL falling edge crossing 30% of V
CC
,
until SDA enters the 30% to 70% of V
CC
window.
0
ns
t
R
(Note 12)
SDA and SCL rise time
From 30% to 70% of V
CC
20 +
0.1 * Cb
250
ns
ISL90727
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