
5
FN8247.4
August 2, 2006
SDA vs SCL Timing
NOTES:
3. Typical values are for T
A
= 25°C and 3.3V supply voltage.
4. LSB: [V(R
W
)
127
– V(R
W
)
0
]
/
127. V(R
W
)
127
and V(R
W
)
0
are V(R
W
) for the DCP register set to FF hex and 00 hex respectively. LSB is the
incremental voltage when changing from one tap to an adjacent tap.
5. ZS error = V(R
W
)
0
/
LSB.
6. FS error = [V(R
W
)
127
– V
CC
]
/
LSB.
7. MI =
|
R
127
– R
0
|
/
127. R
127
and R
0
are the measured resistances for the DCP register set to FF hex and 00 hex respectively.
Roffset = R
0
/
MI, when measuring between R
W
and R
L
.
8. Roffset = R
127
/
MI, when measuring between R
W
and R
H
.
9. RDNL = (R
i
– R
i-1
)
/
MI - 1, for i = 32 to 127.
10. RINL = [R
i
– (MI i) – R
0
]
/
MI, for i = 32 to 127.
6
125°C
11.
for i = 32 to 127, T = -40°C to 85°C. Max( ) is the maximum value of the resistance and Min ( ) is the
minimum value of the resistance over the temperature range.
12. This parameter is not 100% tested.
13. V
IL
= 0V, V
IH
= V
CC.
14. These are I
2
C-specific parameters and are not directly tested. However, they are used in the device testing to validate specifications.
Principles of Operation
The ISL90727 and ISL90728 are integrated circuits
incorporating one DCP with its associated registers and an
I
2
C serial interface providing direct communication between
a host and the potentiometer.
DCP Description
The DCP is implemented with a combination of resistor
elements and CMOS switches. The physical ends of the DCP
are equivalent to the fixed terminals of a mechanical
potentiometer (R
H
and R
L
pins). The R
W
pin of the DCP is
connected to intermediate nodes, and is equivalent to the wiper
terminal of a mechanical potentiometer. The position of the
wiper terminal within the DCP is controlled by a 7-bit volatile
Wiper Register (WR). The DCP has its own WR. When the WR
of the DCP contains all zeroes (WR<6:0> = 00h), its wiper
terminal (R
W
) is closest to its “Low” terminal (R
L
). When the
WR of the DCP contains all ones (WR<6:0> = 7Fh), its wiper
terminal (R
W
) is closest to its “High” terminal (R
H
). As the value
of the WR increases from all zeroes (00h) to all ones (127
decimal), the wiper moves monotonically from the position
closest to R
L
to the position closest to R
H
. At the same time,
the resistance between R
W
and R
L
increases monotonically,
while the resistance between R
H
and R
W
decreases
monotonically. R
L
is connected to the GND pin of the device, so
the wiper movement will always be relative to R
L
.
While the ISL90727 and ISL90728 are being powered up,
the WR is reset to 40h (64 decimal), which locates R
W
roughly at the center between R
L
and R
H
.
t
F
(Note 14)
SDA and SCL Fall Time
From 70% to 30% of V
CC
20 +
0.1 * Cb
250
ns
Cb
(Note 14)
Capacitive Loading of SDA or SCL
Total on-chip and off-chip
10
400
pF
Rpu
(Note 14)
SDA and SCL Bus Pull-up Resistor
Off-chip
Maximum is determined by t
R
and t
F
.
For Cb = 400pF, max is about 2~2.5k
Ω
.
For Cb = 40pF, max is about 15~20k
Ω
1
k
Ω
Operating Specifications
(Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
(Note 3)
MAX
UNIT
t
SU:STO
t
DH
t
HIGH
t
SU:STA
t
HD:STA
t
HD:DAT
t
SU:DAT
SCL
SDA
(INPUT TIMING)
SDA
(OUTPUT TIMING)
t
F
t
LOW
t
BUF
t
AA
t
R
TC
R
Max Ri
+
Min Ri
]
)
)
[
]
2
------------------------------–
----------------
×
=
ISL90727, ISL90728