參數(shù)資料
型號： ISL90726WIE6Z
廠商： INTERSIL CORP
元件分類： 數(shù)字電位計
英文描述： Digitally Controlled Potentiometer (XDCP)
中文描述： 10K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 128 POSITIONS, PDSO6
封裝： LEAD FREE, MO-203-AB, SC-70, 6 PIN
文件頁數(shù)： 4/8頁
文件大小： 226K
代理商： ISL90726WIE6Z
4
FN8244.1
August 3, 2005
SERIAL INTERFACE SPECIFICATIONS
V
IL
SDA, and SCL input buffer LOW
voltage
-0.3
0.3*V
CC
V
V
IH
SDA, and SCL input buffer HIGH
voltage
0.7*V
CC
V
CC
+
0.3
V
Hysteresis
SDA and SCL input buffer hysteresis
0.05*
V
CC
V
V
OL
SDA output buffer LOW voltage,
sinking 4mA
0
0.4
V
Cpin
(Note 10) SDA, and SCL pin capacitance
10
pF
f
SCL
SCL frequency
400
kHz
t
IN
Pulse width suppression time at SDA
and SCL inputs
Any pulse narrower than the max spec is
suppressed.
50
ns
t
AA
SCL falling edge to SDA output data
valid
SCL falling edge crossing 30% of V
CC
, until
SDA exits the 30% to 70% of V
CC
window.
900
ns
t
BUF
Time the bus must be free before the
start of a new transmission
SDA crossing 70% of V
CC
during a STOP
condition, to SDA crossing 70% of V
CC
during
the following START condition.
1300
ns
t
LOW
Clock LOW time
Measured at the 30% of V
CC
crossing.
1300
ns
t
HIGH
Clock HIGH time
Measured at the 70% of V
CC
crossing.
600
ns
t
SU:STA
START condition setup time
SCL rising edge to SDA falling edge. Both
crossing 70% of V
CC
.
600
ns
t
HD:STA
START condition hold time
From SDA falling edge crossing 30% of V
CC
to
SCL falling edge crossing 70% of V
CC
.
600
ns
t
SU:DAT
Input data setup time
From SDA exiting the 30% to 70% of V
CC
window, to SCL rising edge crossing 30% of
V
CC
100
ns
t
HD:DAT
Input data hold time
From SCL rising edge crossing 70% of V
CC
to
SDA entering the 30% to 70% of V
CC
window.
0
ns
t
SU:STO
STOP condition setup time
From SCL rising edge crossing 70% of V
CC
, to
SDA rising edge crossing 30% of V
CC
.
600
ns
t
HD:STO
STOP condition hold time for read, or
volatile only write
From SDA rising edge to SCL falling edge. Both
crossing 70% of V
CC
.
600
ns
t
DH
Output data hold time
From SCL falling edge crossing 30% of V
CC
,
until SDA enters the 30% to 70% of V
CC
window.
0
ns
t
R
(Note 12)
SDA and SCL rise time
From 30% to 70% of V
CC
20 +
0.1 * Cb
250
ns
t
F
(Note 12)
SDA and SCL fall time
From 70% to 30% of V
CC
20 +
0.1 * Cb
250
ns
Cb
(Note 12)
Capacitive loading of SDA or SCL
Total on-chip and off-chip
10
400
pF
Rpu
(Note 12)
SDA and SCL bus pull-up resistor off-
chip
Maximum is determined by t
R
and t
F
.
For Cb = 400pF, max is about 2~2.5k
.
For Cb = 40pF, max is about 15~20k
.
1
k
Operating Specifications
(Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
(Note 1)
MAX
UNIT
ISL90726
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