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參數(shù)資料
| 型號： | ISL88731HRZ |
| 廠商： | INTERSIL CORP |
| 元件分類： | 電源管理 |
| 英文描述： | SMBus Level 2 Battery Charger |
| 中文描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PQCC28 |
| 封裝： | 5 X 5 MM, 0.80 MM HEIGHT, ROHS COMPLIANT, PLASTIC, TQFN-28 |
| 文件頁數(shù)： | 16/22頁 |
| 文件大?。?/td> | 474K |
| 代理商： | ISL88731HRZ |
16
FN9258.0
November 20, 2006
10% of the switching frequency. The highest F
CO
is in
voltage control mode with the battery removed and may be
calculated (approximately) from Equation 5:
Output Capacitor Selection
The output capacitor in parallel with the battery is used to
absorb the high frequency switching ripple current and
smooth the output voltage. The RMS value of the output
ripple current I
rms
is given by Equation 6:
Where the duty cycle D is the ratio of the output voltage
(battery voltage) over the input voltage for continuous
conduction mode which is typical operation for the battery
charger. During the battery charge period, the output voltage
varies from its initial battery voltage to the rated battery
voltage. So, the duty cycle varies from 0.53 for the minimum
battery voltage of 7.5V (2.5V/Cell) to 0.88 for the maximum
battery voltage of 12.6V. The maximum RMS value of the
output ripple current occurs at the duty cycle of 0.5 and is
expressed as Equation 7:
For V
IN,MAX
= 19V, VBAT = 16.8V, L = 10μH, and
f
s
= 400kHz, the maximum RMS current is 0.19A. A typical
20
μ
F ceramic capacitor is a good choice to absorb this
current and also has very small size. Organic polymer
capacitors have high capacitance with small size and have a
significant equivalent series resistance (ESR). Although
ESR adds to ripple voltage, it also creates a high frequency
zero that helps the closed loop operation of the buck
regulator.
EMI considerations usually make it desirable to minimize
ripple current in the battery leads. Beads may be added in
series with the battery pack to increase the battery
impedance at 400kHz switching frequency. Switching ripple
current splits between the battery and the output capacitor
depending on the ESR of the output capacitor and battery
impedance. If the ESR of the output capacitor is 10m
Ω
and
battery impedance is raised to 2
Ω
with a bead, then only
0.5% of the ripple current will flow in the battery.
MOSFET Selection
The Notebook battery charger synchronous buck converter
has the input voltage from the AC adapter output. The
maximum AC adapter output voltage does not exceed 25V.
Therefore, 30V logic MOSFET should be used.
The high side MOSFET must be able to dissipate the
conduction losses plus the switching losses. For the battery
charger application, the input voltage of the synchronous
buck converter is equal to the AC adapter output voltage,
which is relatively constant. The maximum efficiency is
achieved by selecting a high side MOSFET that has the
conduction losses equal to the switching losses. Switching
losses in the low-side FET are very small. The choice of
low-side FET is a trade-off between conduction losses
(r
DS(ON)
) and cost. A good rule of thumb for the r
DS(ON)
of
the low-side FET is 2X the r
DS(ON)
of the high-side FET.
The LGATE gate driver can drive sufficient gate current to
switch most MOSFETs efficiently. However, some FETs may
exhibit cross conduction (or shoot-through) due to current
injected into the drain-to-source parasitic capacitor (C
gd
) by
the high dV/dt rising edge at the phase node when the high
side MOSFET turns on. Although LGATE sink current (1.8A
typical) is more than enough to switch the FET off quickly,
voltage drops across parasitic impedances between LGATE
and the MOSFET can allow the gate to rise during the fast
rising edge of voltage on the drain. MOSFETs with low
threshold voltage (<1.5V) and low ratio of C
gs
/C
gd
(<5) and
high gate resistance (>4
Ω
) may be turned on for a few ns by
the high dV/dt (rising edge) on their drain. This can be
avoided with higher threshold voltage and C
gs
/C
gd
ratio.
Another way to avoid cross conduction is slowing the turn-on
speed of the high-side MOSFET by connecting a resistor
between the BOOT pin and the boot strap cap.
For the high-side MOSFET, the worst-case conduction
losses occur at the minimum input voltage, as shown in
Equation 8:
V
IN
The optimum efficiency occurs when the switching losses
equal the conduction losses. However, it is difficult to
calculate the switching losses in the high-side MOSFET
since it must allow for difficult-to-quantify factors that
influence the turn-on and turn-off times. These factors
include the MOSFET internal gate resistance, gate charge,
threshold voltage, stray inductance and the pull-up and pull-
down resistance of the gate driver.
The following switching loss calculation (Equation 9)
provides a rough estimate.
where the following are the peak gate-drive source/sink
current of Q
1
, respectively:
Q
gd
: drain-to-gate charge,
Q
rr
: total reverse recovery charge of the body-diode in
low-side MOSFET,
I
LV
: inductor valley current,
I
LP
: Inductor peak current,
I
g,sink
I
g
,
source
F
CO
5 11 R
------------------------------------------
=
(EQ. 5)
I
RMS
V
12 L F
SW
-----------------------------------
D
1
D
–
(
)
=
(EQ. 6)
I
RMS
V
,
12 L F
SW
4
-------------------------------------------
=
(EQ. 7)
P
Q1 conduction
---------------
I
BAT
2
r
DS ON
)
=
(EQ. 8)
P
Q1 Switching
1
2
--
V
IN
I
LV
f
sw
Q
g source
,
------------------------
1
2
--
V
IN
I
LP
f
sw
Q
g
,
k
sin
-----------------
Q
rr
V
IN
f
sw
+
+
=
(EQ. 9)
ISL88731
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