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參數(shù)資料
| 型號(hào)： | ISL88708IB831Z |
| 廠商： | INTERSIL CORP |
| 元件分類： | 電源管理 |
| 英文描述： | UP Supervisor with Watchdog Timer,Power-Fail Comparator, Manual Reset and Adjustable Power-On Reset |
| 中文描述： | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO8 |
| 封裝： | ROHS COMPLIANT, PLASTIC, MS-012AA, SOIC-8 |
| 文件頁(yè)數(shù)： | 8/13頁(yè) |
| 文件大?。?/td> | 518K |
| 代理商： | ISL88708IB831Z |
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8
FN8092.0
October 18, 2005
Watchdog Timer
The Watchdog Timer circuit checks microprocessor activity
by monitoring the WDI input pin. The microprocessor must
periodically toggle the WDI pin within t
WDT
(typically 1.6s),
otherwise the WDO pin goes low (see Figure 9). Internally,
the 1.6s timer is cleared by either a reset or by toggling the
WDI input, which can detect pulses longer than 50ns.
Whenever there is a low-voltage V
DD
condition, WDO goes
low. Unlike the reset outputs, however, WDO does not have
a minimum reset pulse width (t
POR
). WDO goes high as
soon as V
DD
rises above its voltage trip point (see Figure 9).
With WDI open or connected to a tristated high impedance
input, the Watchdog Timer is disabled and only pulls low
when V
DD
< V
TH1.
ISL88705EVAL1 and Applications
The ISL88705EVAL1 supports all six of the ISL88705-
ISL88813 devices, enabling evaluation of basic functional
operation and common application implementations.
Figures 11 and 17 illustrate the ISL88705EVAL1 in
photographic and schematic forms respectively.
The ISL88705EVAL1 is divided into two banks; each bank
having one each of the three available pinouts. The top bank
is fully populated and immediately usable whereas the
bottom bank is unpopulated. Samples of other sample
variants can be evaluated singularly or in combination with
any other variant to provide a specific voltage monitoring
solution. The left position has a ISL88705IB846Z monitoring
the V
DD
rail voltage for a minimum of 4.64V with reset
signaling. In addition, the power fail input (PFI) is being
compared to the internal PFI voltage reference of 1.25V and
the power fail output (PFO) will report the PFI condition. This
feature can be used for monitoring an auxiliary voltage,
providing an early warning of a brownout or power failure or
presence detection in a system.
The middle position has the ISL88813IB846Z installed and is
set up as a 5V window detector with jumper J1 installed. The
V
DD
monitors for UV and the PFI for OV via the R3, R4
divider. The PFO output is inverted and connected to the
manual reset input (MR) via U4. Hence a reset signal is
generated when 4.64V < V
DD
> 5.38V. With J1 removed the
PFO will be an OV indicator but no reset signal will be
generated. Both of these positions share a common
Watchdog input (WDI) signal although each has its own
Watchdog output (WDO).
The right position has the ISL88707IB846Z
and is set up as
a +12V and +5V UV monitor with reset signal. The PFI
allows monitoring of any voltage above the 1.25V PFI
reference. The ISL88707 and ISL88708 have the unique
feature of an adjustable time to reset (t
POR
)signal
generation capability via the C
POR
pin with an external
capacitor to GND. This evaluation platform has an adjustable
SMD capacitor, C4 (8pF to 45pF) that allows easy evaluation
of this feature. Also unique to the ISL88707 and ISL88708
are both the RESET and RESET outputs, all other variants
having only one or the other.
FIGURE 9. WATCHDOG TIMING DIAGRAM
V
DD
WDI
WDO
V
TH1
1V
t
POR
t
WDT
>t
WDPS
< t
WDT
< t
WDT
< t
WDT
t
POR
t
RPD
RST
t
POR
ISL88705, ISL88706, ISL88707, ISL88708, ISL88716, ISL88813
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