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參數(shù)資料
| 型號(hào)： | ISL88694IH5Z |
| 廠商： | INTERSIL CORP |
| 元件分類： | 模擬信號(hào)調(diào)理 |
| 英文描述： | SMBus Accelerator (SMA) |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PDSO5 |
| 封裝： | ROHS COMPLIANT, SOT-23, 5 PIN |
| 文件頁(yè)數(shù)： | 5/7頁(yè) |
| 文件大?。?/td> | 247K |
| 代理商： | ISL88694IH5Z |
5
FN8239.1
January 21, 2005
Functional Description
SMBus Overview
The SMBus or I
2
C bus is a 2-wire multimaster bus, meaning
that more than one device connected to the bus is capable of
controlling it. Master devices communicate to other master
or slave devices using one clock and one data line. These
are both bidirectional.
In order to allow multimaster operation without bus
contention, it is necessary to allow each bus to be connected
to a positive supply voltage via a current-source or pull-up
resistor (see “System Diagram” on page 2). When the bus is
free, both lines are HIGH. The output stages of devices
connected to the bus must have an open-drain or open-
collector to perform the wired-AND function.
Simple pull-up resistors on the clock and data lines work well
unless there are long signal lines or many devices
connected to the bus. Then, the combined capacitance of
the bus increases the rise time on the signal to such an
extent that the communication becomes unreliable or fails to
meet the bus timing specifications. Smaller resistors can
sometimes compensate for the extra capacitance, but this
increases the current consumption when the signal lines are
pulled LOW.
FIGURE 5. V
TRIPH
VOLTAGE
FIGURE 6. I
DD
CURRENT. SMBus1=SMBus2=OPEN.
FIGURE 7. BOOST PULL-UP CURRENT vs. SMBus VOLTAGE
Typical Performance Curves
(Continued)
0.50
0.55
0.60
0.65
0.70
0.45
0.40
0.35
0.30
-40
-20
0
20
40
60
80
100
-60
TEMPERATURE (°C)
I
T
D
-
VDD=5.5V
VDD=2.7V
75
80
85
90
95
70
65
60
55
-40
-20
0
20
40
60
80
100
-60
TEMPERATURE (°C)
S
D
VDD=5.5V
VDD=2.7V
2.0
2.5
3.0
3.5
1.5
1.0
0.5
0
1
2
3
4
5
0
SMBus VOLTAGE (V)
B
O
6
VDD=5.0V
VDD=2.7V
ISL88694
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