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參數(shù)資料
| 型號： | ISL88550AIRZ |
| 廠商： | INTERSIL CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | Synchronous Step Down Controller with Sourcing and Sinking LDO Regulator |
| 中文描述： | SWITCHING CONTROLLER, 600 kHz SWITCHING FREQ-MAX, PQCC28 |
| 封裝： | 5 X 5 MM, ROHS COMPLIANT, PLASTIC, MO-220WHHD-1, TQFN-28 |
| 文件頁數(shù)： | 24/25頁 |
| 文件大?。?/td> | 928K |
| 代理商： | ISL88550AIRZ |
24
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Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6168.0
October 12, 2005
where V
DROP1
and V
DROP2
are the parasitic voltage drops
in the discharge and charge paths (see the On- Time One-
Shot (T
ON
) section), t
OFF(MIN)
is from the Electrical
Characteristics, and K is taken from Table 1. The absolute
minimum input voltage is calculated with h = 1.
If the calculated V
IN(MIN)
is greater than the required
minimum input voltage, then operating frequency must be
reduced or output capacitance added to obtain an
acceptable V
SAG
. If operation near dropout is anticipated,
calculate V
SAG
to be sure of adequate transient response.
A dropout design example follows:
V
OUT
= 2.5V
f
SW
= 600kHz
K = 1.7μs
t
OFF(MIN)
= 450ns
V
DROP1
= V
DROP2
= 100mV
h = 1.5
PC Board Layout Guidelines
Careful PC board layout is critical to achieve low switching
losses and clean, stable operation. The switching power
stage requires particular attention. If possible, mount all of
the power components on the topside of the board, with their
ground terminals flush against one another. Follow these
guidelines for good PC board layout:
Keep the high-current paths short, especially at the
ground terminals. This practice is essential for stable,
jitter-free operation.
Keep the power traces and load connections short. This
practice is essential for high efficiency. Using thick copper
PC boards (2oz vs. 1oz) can enhance full-load efficiency
by 1% or more. Correctly routing PC board traces is a
difficult task that must be approached in terms of fractions
of centimeters, where a single m of excess trace
resistance causes a measurable efficiency penalty.
Minimize current-sensing errors by connecting CSP and
CSN directly across the current-sense resistor (R
SENSE
).
When trade-offs in trace lengths must be made, it is
preferable to allow the inductor-charging path to be made
longer than the discharge path. For example, it is better to
allow some extra distance between the input capacitors
and the high-side MOSFET than to allow distance
between the inductor and the low side MOSFET or
between the inductor and the output filter capacitor.
Route high-speed switching nodes (BOOT, PHASE,
UGATE, and LGATE) away from sensitive analog areas
(REF, FB, and ILIM).
Special Layout Considerations for LDO Section
The 20μF output cap (or caps) at VTT should be placed as
close to the VTT and PGND2 pins (pins 12 and 11) as
possible to minimize the series resistance/inductance in the
trace. The PGND2 side of the cap should be shorted with the
lowest impedance path to the ground slug underneath the
IC, which should also be star-connected to the GND (pin 24)
of the IC. A narrower trace can be used to tie the output
voltage on the VTT side of the cap back to the VTTS pin
(pin 9). However, keep this trace well away from noisy
signals such as the PGND or PGND2 to prevent noise from
being injected into the error amplifier’s input. For best
performance, the VTTI bypass cap should also be placed as
close to the VTTI pin (pin 13) as possible. A short low
impedance connection should also be made to tie the other
side of the cap to the PGND2 pin. The REFIN pin (pin 14)
should be separately routed with a clean trace and
adequately bypass to AGND. A suggested layout of the
board can be found in Evaluation Board Kit of ISL88550A.
(
)
V
3
V
1
V
1
μs
7
ns
450
5
1
V
1
V
5
V
MIN
IN
=
+
×
+
=
ISL88550A
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