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參數(shù)資料
| 型號： | ISL8540 |
| 廠商： | Intersil Corporation |
| 元件分類： | 基準(zhǔn)電壓源/電流源 |
| 英文描述： | DC/DC Power Switching Regulator |
| 中文描述： | DC/DC電源開關(guān)穩(wěn)壓器 |
| 文件頁數(shù)： | 14/16頁 |
| 文件大?。?/td> | 952K |
| 代理商： | ISL8540 |
14
FN6495.4
September 18, 2007
the modulator is simply the input voltage (V
IN
) divided by the
peak-to-peak oscillator voltage
Δ
V
OSC
. The ISL8540
incorporates a feed forward loop that accounts for changes
in the input voltage. This maintains a constant modulator
gain.
Modulator Break Frequency Equations
The compensation network consists of the transconductance
amplifier (internal to the ISL8540) and the impedance
networks Z
IN
and Z
FB
. The goal of the compensation
network is to provide a closed loop transfer function with the
highest 0dB crossing frequency (f
0dB
) and adequate phase
margin. Phase margin is the difference between the closed
loop phase at f
0dB
and 180°. The equations in the following
section relate the compensation network’s poles, zeros and
gain to the components (R
2
, R
3
, R
4
, R
6
, C
10
, C
6
, and C
7
) in
Figure 28. Use these guidelines for locating the poles and
zeros of the compensation network:
1. Pick Gain (R
3
gm/(R
2
+R
3
) for desired converter
bandwidth.
2. Place 1
ST
Zero Below Filter’s Double Pole (~75% f
LC
).
3. Place 2
ND
Zero at Filter’s Double Pole.
4. Place 1
ST
Pole at the ESR Zero.
5. Place 2
ND
Pole at Half the Switching Frequency.
6. Check Gain against Error transconductance’s Open-
Loop Gain.
7. Estimate Phase Margin - Repeat if Necessary.
Compensation Break Frequency
Equations
g
m
π
R
2
C
7
Assumption: R6<<R2, R6<<R3, and C10<<C6.
Figure 29 shows an asymptotic plot of the DC/DC converter’s
gain vs frequency. The actual Modulator Gain has a high gain
peak due to the high Q factor of the output filter and is not
shown in Figure 29. Using the guidelines on page 13 should
give a Compensation Gain similar to the curve plotted. The
open loop error amplifier gain bounds the compensation gain.
Check the compensation gain at f
P2
with the capabilities of
the error amplifier. The Closed Loop Gain is constructed on
the graph of Figure 29 by adding the Modulator Gain (in dB) to
the Compensation Gain (in dB). This is equivalent to
multiplying the modulator transfer function to the
compensation transfer function and plotting the gain.
The compensation gain uses external impedance networks
Z
FB
and Z
IN
to provide a stable, high bandwidth (BW) overall
loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45°.
Include worst case component variations when determining
phase margin.
A more detailed explanation of voltage mode control of a
buck regulator can be found in Tech Brief TB417, titled
“Designing Stable Compensation Networks for Single Phase
Voltage Mode Buck Regulators.”
Layout Considerations
Layout is very important in high frequency switching
converter design. With power devices switching efficiently
+
-
FIGURE 28. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN AND OUTPUT
VOLTAGE SELECTION
V
OUT
REFERENCE
L
O
C
O
ESR
V
IN
Δ
V
OSC
ERROR
AMP
PWM
DRIVER
(PARASITIC)
Z
FB
REFERENCE
R
2
R
6
R
4
C
7
C
10
C
6
COMP
V
OUT
FB
Z
FB
ISL8540
Z
IN
COMPARATOR
DRIVER
DETAILED COMPENSATION COMPONENTS
LX
V
E/A
+
-
+
-
Z
IN
OSC
R
3
V
OUT
1.20
1
R
2
R
3
------
+
×
=
g
m
D
fLC
2
π
x LO x CO
--------------------1
=
fESR
π
x ESR x CO
2
=
(EQ. 11)
f
Z1
2
π
1
+
---------------------------------
C
6
)
-------------R
=
f
Z2
2
=
f
P1
π
R
6
C
7
2
=
f
P2
π
R
4
C
10
2
=
(EQ. 12)
100
80
60
40
20
0
-20
-40
-60
F
P1
F
Z2
10M
1M
100k
10k
1k
100
10
OPEN LOOP
ERROR AMP GAIN
F
Z1
F
P2
20LOG
(R
4
/R
2
)
F
LC
F
ESR
COMPENSATION
GAIN
CLOSED LOOP
GAIN
G
FREQUENCY (Hz)
20LOG
(V
IN
/
Δ
V
OSC
)
MODULATOR
GAIN
FIGURE 29. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
ISL8540
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