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參數(shù)資料
| 型號： | ISL84582 |
| 廠商： | Intersil Corporation |
| 英文描述： | Low-Voltage, Single and Dual Supply, Differential 4 to 1 Multiplexer(低電壓, 單/雙電源, 差分4合1多路復(fù)用器) |
| 中文描述： | 低電壓，單和雙電源，差分4至1多路復(fù)用器（低電壓，單/雙電源，差分4合1多路復(fù)用器） |
| 文件頁數(shù)： | 14/14頁 |
| 文件大小： | 450K |
| 代理商： | ISL84582 |
14
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6213.1
January 27, 2006
ISL84582
Thin Shrink Small Outline Plastic Packages (TSSOP)
NOTES:
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AB, Issue E.
2. Dimensioning and tolerancing per ANSI Y14.5M
-
1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.15mm (0.006
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total in excess
of “b” dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are not necessarily exact. (Angles in degrees)
α
INDEX
AREA
E1
D
N
1
2
3
-B-
0.10(0.004)
C A
M
B S
e
-A-
b
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
c
E
0.25(0.010)
B
M
M
L
0.25
0.010
GAUGE
PLANE
A2
0.05(0.002)
M16.173
16 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE
SYMBOL
INCHES
MILLIMETERS
NOTES
MIN
MAX
MIN
MAX
A
-
0.043
-
1.10
-
A1
0.002
0.006
0.05
0.15
-
A2
0.033
0.037
0.85
0.95
-
b
0.0075
0.012
0.19
0.30
9
c
0.0035
0.008
0.09
0.20
-
D
0.193
0.201
4.90
5.10
3
E1
0.169
0.177
4.30
4.50
4
e
0.026 BSC
0.65 BSC
-
E
0.246
0.256
6.25
6.50
-
L
0.020
0.028
0.50
0.70
6
N
α
16
16
7
0
o
8
o
0
o
8
o
-
Rev. 1 2/02
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| ISL84582IVZ | 功能描述:IC MUX/DEMUX DUAL 4X1 16TSSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 模擬開關(guān)，多路復(fù)用器，多路分解器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:36 系列:- 功能:多路復(fù)用器 電路:2 x 4:1 導(dǎo)通狀態(tài)電阻:75 歐姆 電壓電源:單/雙電源 電壓 - 電源，單路/雙路(±):2 V ~ 12 V，±2 V ~ 6 V 電流 - 電源:- 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:20-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:20-SOIC W 包裝:管件 |
| ISL84582IVZ-T | 功能描述:IC MUX/DEMUX DUAL 4X1 16TSSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 模擬開關(guān)，多路復(fù)用器，多路分解器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:36 系列:- 功能:多路復(fù)用器 電路:2 x 4:1 導(dǎo)通狀態(tài)電阻:75 歐姆 電壓電源:單/雙電源 電壓 - 電源，單路/雙路(±):2 V ~ 12 V，±2 V ~ 6 V 電流 - 電源:- 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:20-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:20-SOIC W 包裝:管件 |
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| ISL84684_07 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Ultra Low ON-Resistance, Low Voltage, Single Supply, Dual SPDT Analog Switch |
| ISL84684II | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Ultra Low ON-Resistance, Low Voltage, Single Supply, Dual SPDT Analog Switch in Chipscale Package |
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