參數(shù)資料
型號: ISL83483IP
廠商: INTERSIL CORP
元件分類: 通用總線功能
英文描述: Quadruple 2-Input Positive-OR Gates 14-SOIC -40 to 85
中文描述: LINE TRANSCEIVER, PDIP8
封裝: PLASTIC, MS-001BA, DIP-8
文件頁數(shù): 9/17頁
文件大?。?/td> 536K
代理商: ISL83483IP
9
FIGURE 3A. TEST CIRCUIT
FIGURE 3B. MEASUREMENT POINTS
FIGURE 3. DRIVER ENABLE AND DISABLE TIMES (EXCLUDING ISL83488, ISL83490)
FIGURE 4A. TEST CIRCUIT
FIGURE 4B. MEASUREMENT POINTS
FIGURE 4. RECEIVER PROPAGATION DELAY
FIGURE 5A. TEST CIRCUIT
FIGURE 5B. MEASUREMENT POINTS
FIGURE 5. RECEIVER ENABLE AND DISABLE TIMES (EXCLUDING ISL83488, ISL83490)
Test Circuits and Waveforms
(Continued)
D
DE
DI
Z
Y
V
CC
GND
SW
PARAMETER
OUTPUT
RE
DI
SW
t
HZ
t
LZ
t
ZH
t
ZL
t
ZH(SHDN)
t
ZL(SHDN)
Y/Z
X
1/0
GND
Y/Z
X
0/1
V
CC
GND
Y/Z
0 (Note 5)
1/0
Y/Z
0 (Note 5)
0/1
V
CC
GND
Y/Z
1 (Note 8)
1/0
Y/Z
1 (Note 8)
0/1
V
CC
SIGNAL
GENERATOR
110
C
L
= 50pF
OUT (Y, Z)
3V
0V
1.5V
1.5V
V
OH
0V
V
OH
- 0.25V
t
HZ
OUT (Y, Z)
V
CC
V
OL
V
OL
+ 0.25V
t
LZ
DE
OUTPUT HIGH
OUTPUT LOW
t
ZL
, t
ZL(SHDN)
NOTE 7
t
ZH
, t
ZH(SHDN)
NOTE 7
NOTE 7
50%
50%
SIGNAL
GENERATOR
R
RO
RE
A
B
GND
+1.5V
15pF
RO
3V
0V
t
PLH
1.5V
1.5V
V
CC
0V
50%
50%
t
PHL
A
1k
V
CC
GND
SW
PARAMETER
DE
0
A
SW
GND
t
HZ
t
LZ
t
ZH
(Note 6)
t
ZL
(Note 6)
t
ZH(SHDN)
(Note 9)
t
ZL(SHDN)
(Note 9)
+1.5V
0
-1.5V
V
CC
GND
0
+1.5V
0
-1.5V
V
CC
GND
0
+1.5V
0
-1.5V
V
CC
SIGNAL
GENERATOR
R
RO
RE
A
B
GND
15pF
RO
3V
0V
1.5V
1.5V
V
OH
0V
1.5V
V
OH
- 0.25V
t
HZ
RO
V
CC
V
OL
1.5V
V
OL
+ 0.25V
t
LZ
RE
OUTPUT HIGH
OUTPUT LOW
t
ZL
, t
ZL(SHDN)
NOTE 7
t
ZH
, t
ZH(SHDN)
NOTE 7
NOTE 7
ISL83483, ISL83485, ISL83488, ISL83490, ISL83491
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