
9
FIGURE 3A. TEST CIRCUIT
FIGURE 3B. MEASUREMENT POINTS
FIGURE 3. DRIVER ENABLE AND DISABLE TIMES (EXCLUDING ISL83488, ISL83490)
FIGURE 4A. TEST CIRCUIT
FIGURE 4B. MEASUREMENT POINTS
FIGURE 4. RECEIVER PROPAGATION DELAY
FIGURE 5A. TEST CIRCUIT
FIGURE 5B. MEASUREMENT POINTS
FIGURE 5. RECEIVER ENABLE AND DISABLE TIMES (EXCLUDING ISL83488, ISL83490)
Test Circuits and Waveforms (Continued)
D
DE
DI
Z
Y
VCC
GND
SW
PARAMETER
OUTPUT
RE
DI
SW
tHZ
Y/Z
X
1/0
GND
tLZ
Y/Z
X
0/1
VCC
tZH
Y/Z
0 (Note 5)
1/0
GND
tZL
Y/Z
0 (Note 5)
0/1
VCC
tZH(SHDN)
Y/Z
1 (Note 8)
1/0
GND
tZL(SHDN)
Y/Z
1 (Note 8)
0/1
VCC
SIGNAL
GENERATOR
110
CL = 50pF
OUT (Y, Z)
3V
0V
1.5V
VOH
0V
VOH - 0.25V
tHZ
OUT (Y, Z)
VCC
VOL
VOL + 0.25V
tLZ
DE
OUTPUT HIGH
OUTPUT LOW
tZL, tZL(SHDN)
tZH, tZH(SHDN)
NOTE 7
50%
NOTE 7
SIGNAL
GENERATOR
R
RO
RE
A
B
GND
+1.5V
15pF
RO
3V
0V
tPLH
1.5V
VCC
0V
50%
tPHL
A
1k
VCC
GND
SW
PARAMETER
DE
A
SW
tHZ
0
+1.5V
GND
tLZ
0-1.5V
VCC
tZH (Note 6)
0
+1.5V
GND
tZL (Note 6)
0
-1.5V
VCC
tZH(SHDN) (Note 9)
0
+1.5V
GND
tZL(SHDN) (Note 9)
0
-1.5V
VCC
SIGNAL
GENERATOR
R
RO
RE
A
B
GND
15pF
RO
3V
0V
1.5V
VOH
0V
1.5V
VOH - 0.25V
tHZ
RO
VCC
VOL
1.5V
VOL + 0.25V
tLZ
RE
OUTPUT HIGH
OUTPUT LOW
tZL, tZL(SHDN)
tZH, tZH(SHDN)
NOTE 7
ISL83483, ISL83485, ISL83488, ISL83490, ISL83491