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參數(shù)資料
型號： ISL81487IB-T
廠商： Intersil
文件頁數(shù)： 9/13頁
文件大小： 0K
描述： IC TXRX RS485/422 5V HS 8-SOIC
標準包裝： 2,500
類型： 收發(fā)器
驅(qū)動器/接收器數(shù)： 1/1
規(guī)程： RS422，RS485
電源電壓： 4.5 V ~ 5.5 V
安裝類型： 表面貼裝
封裝/外殼： 8-SOIC（0.154"，3.90mm 寬）
供應商設(shè)備封裝： 8-SOICN
包裝： 帶卷 (TR)
5
FN6050.7
July 31, 2006
Receiver Input Resistance
RIN
-7V
≤ VCM ≤ 12V
ISL81483, ISL81487
Full
96
-
k
Ω
ISL8487
Full
48
-
k
Ω
No-Load Supply Current, (Note 3)
ICC
ISL81487, DI, RE = 0V
or VCC
DE = VCC
Full
-
400
500
μA
DE = 0V
Full
-
350
420
μA
ISL8487, ISL81483, DI,
RE = 0V or VCC
DE = VCC
Full
-
160
200
μA
DE = 0V
Full
-
120
145
μA
Shutdown Supply Current
ISHDN
(Note 7), DE = 0V, RE = VCC, DI = 0V or VCC
Full
-
0.5
8
μA
Driver Short-Circuit Current,
VO = High or Low
IOSD1
DE = VCC, -7V ≤ VY or VZ ≤ 12V, (Note 4)
Full
35
-
250
mA
Receiver Short-Circuit Current
IOSR
0V
≤ V
O ≤ VCC
Full
7
-
85
mA
SWITCHING CHARACTERISTICS (ISL81487)
Driver Input to Output Delay
tPLH, tPHL RDIFF = 54Ω, CL = 100pF, (Figure 2)
Full
15
24
50
ns
Driver Output Skew
tSKEW
RDIFF = 54Ω, CL = 100pF, (Figure 2)
Full
-
2
10
ns
Driver Differential Rise or Fall Time
tR, tF
RDIFF = 54Ω, CL = 100pF, (Figure 2)
Full
3
12
25
ns
Driver Enable to Output High
tZH
CL = 100pF, SW = GND, (Figure 3)
Full
-
14
70
ns
Driver Enable to Output Low
tZL
CL = 100pF, SW = VCC, (Figure 3)
Full
-
14
70
ns
Driver Disable from Output High
tHZ
CL = 15pF, SW = GND, (Figure 3)
Full
-
44
70
ns
Driver Disable from Output Low
tLZ
CL = 15pF, SW = VCC, (Figure 3)
Full
-
21
70
ns
Receiver Input to Output Delay
tPLH, tPHL (Figure 4)
Full
30
90
150
ns
Receiver Skew | tPLH - tPHL |tSKD
(Figure 4)
25
-
5
-
ns
Receiver Enable to Output High
tZH
CL = 15pF, SW = GND, (Figure 5)
Full
-
9
50
ns
Receiver Enable to Output Low
tZL
CL = 15pF, SW = VCC, (Figure 5)
Full
-
9
50
ns
Receiver Disable from Output High
tHZ
CL = 15pF, SW = GND, (Figure 5)
Full
-
9
50
ns
Receiver Disable from Output Low
tLZ
CL = 15pF, SW = VCC, (Figure 5)
Full
-
9
50
ns
Maximum Data Rate
fMAX
Full
5
-
Mbps
SWITCHING CHARACTERISTICS (ISL8487, ISL81483)
Driver Input to Output Delay
tPLH, tPHL RDIFF = 54Ω, CL = 100pF, (Figure 2)
Full
250
650
2000
ns
Driver Output Skew
tSKEW
RDIFF = 54Ω, CL = 100pF, (Figure 2)
Full
-
160
800
ns
Driver Differential Rise or Fall Time
tR, tF
RDIFF = 54Ω, CL = 100pF, (Figure 2)
Full
250
900
2000
ns
Driver Enable to Output High
tZH
CL = 100pF, SW = GND, (Figure 3, Note 5)
Full
250
1000
2000
ns
Driver Enable to Output Low
tZL
CL = 100pF, SW = VCC, (Figure 3, Note 5)
Full
250
860
2000
ns
Driver Disable from Output High
tHZ
CL = 15pF, SW = GND, (Figure 3)
Full
300
660
3000
ns
Driver Disable from Output Low
tLZ
CL = 15pF, SW = VCC, (Figure 3)
Full
300
640
3000
ns
Receiver Input to Output Delay
tPLH, tPHL (Figure 4)
Full
250
500
2000
ns
Receiver Skew | tPLH - tPHL |tSKD
(Figure 4)
25
-
60
-
ns
Receiver Enable to Output High
tZH
CL = 15pF, SW = GND, (Figure 5, Note 6)
Full
-
10
50
ns
Receiver Enable to Output Low
tZL
CL = 15pF, SW = VCC, (Figure 5, Note 6)
Full
-
10
50
ns
Receiver Disable from Output High
tHZ
CL = 15pF, SW = GND, (Figure 5)
Full
-
10
50
ns
Receiver Disable from Output Low
tLZ
CL = 15pF, SW = VCC, (Figure 5)
Full
-
10
50
ns
Maximum Data Rate
fMAX
Full
250
-
kbps
Time to Shutdown
tSHDN
(Note 7)
Full
50
120
600
ns
Electrical Specifications
Test Conditions: VCC = 4.5V to 5.5V; Unless Otherwise Specified. Typicals are at VCC = 5V, TA = 25°C,
(Note 2) (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
TEMP
(°C)
MIN
TYP
MAX
UNITS
ISL8487, ISL81483, ISL81487
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