參數(shù)資料
型號(hào)： ISL81387
廠商： Intersil Corporation
英文描述： ±15kV ESD Protected, Dual Protocol (RS-232/RS-485) Transceivers(±15kV ESD保護(hù)，雙協(xié)議(RS-232/RS-485)收發(fā)器)
中文描述： ± 15kV的ESD保護(hù)，雙協(xié)議（RS-232/RS-485）收發(fā)器（± 15kV的ESD保護(hù)，雙協(xié)議（RS-232/RS-485）收發(fā)器）
文件頁(yè)數(shù)： 17/27頁(yè)
文件大小： 1092K
代理商： ISL81387
17
FN6201.1
December 20, 2005
These loopback receivers are not standards compliant, so
the loopback mode can’t be used to implement a half-duplex
RS-485 transceiver.
ISL41387 (QFN Package) Special Features
Logic Supply (V
L
Pin)
The ISL41387 (QFN) includes a V
L
pin that powers the logic
inputs (Tx inputs and control pins) and Rx outputs. These
pins interface with “l(fā)ogic” devices such as UARTs, ASICs,
and
μ
controllers, and today most of these devices use power
supplies significantly lower than 5V. Thus, a 5V output level
from a 5V powered dual protocol IC might seriously
overdrive and damage the logic device input. Similarly, the
the logic device’s low V
OH
might not exceed the V
IH
of a 5V
powered dual protocol input. Connecting the V
L
pin to the
power supply of the logic device - as shown in Figure 11 -
limits the ISL41387’s Rx output V
OH
to V
L
(see Figure 14),
and reduces the Tx and control input switching points to
values compatible with the logic device output levels.
Tailoring the logic pin input switching points and output levels
to the supply voltage of the UART, ASIC, or
μ
controller
eliminates the need for a level shifter/translator between the
two ICs.
V
L
can be anywhere from V
CC
down to 1.65V, but the input
switching points may not provide enough noise margin when
V
L
< 1.8V. Table 5 indicates typical V
IH
and V
IL
values for
various V
L
values so the user can ascertain whether or not a
particular V
L
voltage meets his needs.
The V
L
supply current (I
L
) is typically less than 60
μ
A, as
shown in Figures 19 and 20. All of the DC V
L
current is due
to inputs with internal pull-up resistors (SPB, SLEW, RXEN)
being driven to the low input state. The worst case I
L
current
occurs when all three of the inputs are low (see Figure 19),
due to the I
L
through the pull-up resistors. I
IL
through an
input pull-up resistor is ~20
μ
A, so the I
L
in Figure 19 drops
by about 40
μ
A (at V
L
= 5V) when the SPB is high and 232
mode disables the SLEW pin pull-up (middle vs. top curve).
When all three inputs are driven high, I
L
drops to ~10nA, so
to minimize power dissipation drive these inputs high when
unneeded (e.g., SPB isn’t used in RS-232 mode, so drive it
high).
Active Low Rx Enable (RXEN)
In many RS-485 applications, especially half duplex
configurations, users like to accomplish “echo cancellation”
by disabling the corresponding receiver while its driver is
transmitting data. This function is available on the QFN
package via an active low RXEN pin. The active low function
also simplifies direction control, by allowing a single Tx/Rx
direction control line. If the active high RXEN were used,
either two valuable I/O pins would be used for direction
control, or an external inverter is required between DEN and
RXEN. Figure 12 details the advantage of using the RXEN
pin. When using RXEN, ensure that RXEN is tied to GND.
RS-485 Slew Rate Limited Data Rates
The ISLX1387 FAST speed option (SLEW = High) utilizes Tx
output transitions optimized for a 20Mbps data rate. These
fast edges may increase EMI and reflection issues, even
though fast transitions aren’t required at the lower data rates
used by many applications. With the SLEW pin low, both
product types switch to a moderately slew rate limited output
transition targeted for 460kbps (MED) data rates. The
ISL41387 (QFN version) offers an additional, slew rate
limited data rate that is optimized for 115kbps (SLOW), and
is selected when SLEW = 0 and SPB = 0 (see Table 3). The
slew limited edges permit longer unterminated networks, or
longer stubs off terminated busses, and help minimize EMI
and reflections. Nevertheless, for the best jitter performance
when driving long cables, the faster speed options may be
preferable, even at lower data rates. The faster output
transitions deliver less variability (jitter) when loaded with the
FIGURE 11. USING V
L
PIN TO ADJUST LOGIC LEVELS
GND
R
XD
T
XD
V
CC
= +2V
UART/PROCESSOR
GND
R
A
D
Y
V
CC
= +5V
ISL81387
V
OH
≤
2V
V
OH
= 5V
V
IH
≥
2V
ESD
DIODE
GND
R
XD
T
XD
V
CC
= +2V
UART/PROCESSOR
GND
R
A
D
Y
V
CC
= +5V
ISL41387
V
OH
≤
2V
V
OH
= 2V
V
IH
= 0.9V
ESD
DIODE
V
L
TABLE 5. V
IH
AND V
IL
vs. V
L
FOR V
CC
= 5V
V
L
(V)
V
IH
(V)
V
IL
(V)
1.65V
0.79
0.50
1.8V
0.82
0.60
2.0V
0.87
0.69
2.5V
0.99
0.86
3.3V
1.19
1.05
ISL81387, ISL41387
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ISL81387_07 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:【15kV ESD Protected, 5V, Dual Protocol (RS-232/RS-485) Transceivers
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