參數(shù)資料
型號: ISL8102IRZ
廠商: INTERSIL CORP
元件分類: 穩(wěn)壓器
英文描述: Two-Phase Buck PWM Controller with High Current Integrated MOSFET Drivers
中文描述: SWITCHING CONTROLLER, PQCC32
封裝: 5 X 5 MM, ROHS COMPLIANT, PLASTIC, MO-220VHHD-2, MLFP-32
文件頁數(shù): 13/27頁
文件大小: 711K
代理商: ISL8102IRZ
13
FN9247.0
October 19, 2005
If the R-C network components are selected such that the
R-C time constant matches the inductor L/DCR time
constant, then V
DROOP
is equal to the sum of the voltage
drops across the individual DCRs, multiplied by a gain. As
Equation 8 shows, V
DROOP
is therefore proportional to the
total output current, I
OUT
.
R
R
S
By simply adjusting the value of R
S
, the load line can be set
to any level, giving the converter the right amount of droop at
all load currents. It may also be necessary to compensate for
any changes in DCR due to temperature. These changes
cause the load line to be skewed, and cause the R-C time
constant to not match the L/DCR time constant. If this
becomes a problem a simple negative temperature
coefficient resistor network can be used in the place of
R
COMP
to compensate for the rise in DCR due to
temperature.
Output Voltage Offset Programming
The ISL8102 allows the designer to accurately adjust the
offset voltage by connecting a resistor, R
OFS
, from the OFS
pin to VCC or GND. When R
OFS
is connected between OFS
and VCC, the voltage across it is regulated to 1.5V. This
causes a proportional current (I
OFS
) to flow into the OFS pin
and out of the FB pin. If R
OFS
is connected to ground, the
voltage across it is regulated to 0.5V, and I
OFS
flows into the
FB pin and out of the OFS pin. The offset current flowing
through the resistor between VDIFF and FB will generate the
desired offset voltage which is equal to the product (I
OFS
x
R
1
). These functions are shown in Figures 8 and 9.
Once the desired output offset voltage has been determined,
use the following formulas to set R
OFS
:
For Positive Offset (connect R
OFS
to GND):
0.5 R
V
OFFSET
For Negative Offset (connect R
OFS
to VCC):
1.5 R
OFFSET
V
DROOP
--------------------
I
OUT
DCR
=
(EQ. 8)
FIGURE 7. DCR SENSING CONFIGURATION
-
+
ICOMP
DCR
L
INDUCTOR
IL
1
V
OUT
C
OUT
-
+V
L
(s)
DCR
L
INDUCTOR
IL
2
PHASE1
PHASE2
R
S
R
S
R
COMP
C
COMP
ISUM
IREF
ISL8102
-
+
V
DROOP
I
OUT
DROOP
C
SUM
(Optional)
(EQ. 9)
R
OFS
--------------------------
=
(EQ. 10)
R
OFS
--------------------------
=
E/A
FB
OFS
VCC
GND
+
-
+
-
0.5V
1.5V
GND
R
OFS
R
1
VDIFF
ISL8102
FIGURE 8. POSITIVE OFFSET OUTPUT VOLTAGE
PROGRAMMING
VREF
V
OFS
-
+
I
OFS
E/A
FB
OFS
VCC
GND
+
-
+
-
0.5V
1.5V
VCC
R
OFS
R
1
VDIFF
ISL8102
VREF
V
OFS
+
-
I
OFS
FIGURE 9. NEGATIVE OFFSET OUTPUT VOLTAGE
PROGRAMMING
ISL8102
相關(guān)PDF資料
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