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參數(shù)資料
| 型號(hào)： | ISL8011 |
| 廠商： | Intersil Corporation |
| 英文描述： | 1.2A Integrated FETs, High Efficiency Synchronous Buck Regulator(1.2A集成FETs, 高效同步降壓調(diào)節(jié)器) |
| 中文描述： | 1.2A的集成FET，高效率同步降壓穩(wěn)壓器（1.2A的集成FET的高效同步降壓調(diào)節(jié)器） |
| 文件頁(yè)數(shù)： | 10/10頁(yè) |
| 文件大?。?/td> | 296K |
| 代理商： | ISL8011 |
10
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN9254.1
November 6, 2007
ISL8011
Dual Flat No-Lead Plastic Package (DFN)
//
NX (b)
SECTION "C-C"
FOR ODD TERMINAL/SIDE
e
C C
5
C
TERMINAL TIP
(A1)
BOTTOM VIEW
A
6
AREA
INDEX
C
C
0.10
0.08
SIDE VIEW
0.10
2X
E
A
B
C
0.10
D
TOP
VIEW
C B
2X
6
8
AREA
INDEX
NX L
E2
E2/2
REF.
e
(Nd-1)Xe
N
(DATUM A)
(DATUM B)
5
0.10
8
7
D2
B
A
C
N-1
1
2
PLANE
SEATING
C
A
A3
NX b
D2/2
NX k
9L
M
L10.3x3C
10 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE
SYMBOL
MILLIMETERS
NOTES
MIN
NOMINAL
MAX
A
0.85
0.90
0.95
-
A1
-
-
0.05
-
A3
0.20 REF
-
b
0.20
0.25
0.30
5, 8
D
3.00 BSC
-
D2
2.33
2.38
2.43
7, 8
E
3.00 BSC
-
E2
1.59
1.64
1.69
7, 8
e
0.50 BSC
-
k
0.20
-
-
-
L
0.35
0.40
0.45
8
N
10
2
Nd
5
3
Rev. 1 4/06
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd refers to the number of terminals on D.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.
9. COMPLIANT TO JEDEC MO-229-WEED-3 except for
dimensions E2 & D2.
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