參數(shù)資料
型號(hào): ISL6744AUZ
廠商: INTERSIL CORP
元件分類: 穩(wěn)壓器
英文描述: Octal Buffers/Drivers With 3-State Outputs 20-SOIC -40 to 85
中文描述: 1 A SWITCHING CONTROLLER, 2000 kHz SWITCHING FREQ-MAX, PDSO8
封裝: GREEN, PLASTIC, MO-187AA, MSOP-8
文件頁(yè)數(shù): 13/18頁(yè)
文件大?。?/td> 403K
代理商: ISL6744AUZ
13
FN9147.8
September 22, 2005
based on the nature of the intended load, multiple buck
regulators. To minimize the output impedance of the filter, a
SANYO OSCON 16SH150M capacitor in parallel with a
22
μ
F ceramic capacitor were selected.
Current Limit Threshold
The current limit threshold is fixed at 0.6V nominal, which is
the reference to the overcurrent protection comparator. The
current level that corresponds to the overcurrent threshold
must be chosen to allow for the dynamic behavior of an open
loop converter. In particular, the low inductor ripple current
under steady state operation increases significantly as the
duty cycle decreases.
Figures 8 and 9 show the behavior of the inductor ripple
under steady state and overcurrent conditions. In this
example, the peak current limit is set at 11A. The peak
current limit causes the duty cycle to decrease resulting in a
reduction of the average current through the inductor. The
implication is that the converter can not supply the same
output current in current limit that it can supply under steady
state conditions. The peak current limit setpoint must take
this behavior into consideration. A 5.11
current sense
resistor was selected for the rectified secondary of current
transformer T2 for the ISL6744Eval 1, corresponding to a
peak current limit setpoint of about 11A.
Performance
The major performance criteria for the converter are
efficiency, and to a lesser extent, load regulation. Efficiency,
load regulation and line regulation performance are
demonstrated in the following Figures.
As expected, the output voltage varies considerably with line
and load when compared to an equivalent converter with a
closed loop feedback. However, for applications where tight
regulation is not required, such as those applications that
use downstream DC/DC converters, this design approach is
viable.
FIGURE 8. STEADY STATE SECONDARY WINDING
VOLTAGE AND INDUCTOR CURRENT
14
13
12
11
10
9
8
0.9950
0.9960
0.9970
0.9980
0.9990
1.000
TIME (ms)
V (L1:1)
I
(L1)
FIGURE 9. SECONDARY WINDING VOLTAGE AND
INDUCTOR CURRENT DURING CURRENT LIMIT
OPERATION
V (L1:1)
I
(L1)
0.986
0.988
0.990
0.992
0.994
1.000
TIME (ms)
0.996
0.998
15
10
5
FIGURE 10. EFFICIENCY vs LOAD V
IN
= 48V
100
95
90
85
85
70
0
2
3
4
5
6
7
8
9
10
LOAD CURRENT (A)
E
1
75
FIGURE 11. LOAD REGULATION AT V
IN
= 48V
12.5
12.25
12
11.75
11.5
11
0
2
3
4
5
6
7
8
9
10
LOAD CURRENT (A)
O
1
11.25
ISL6744
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