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參數(shù)資料
| 型號： | ISL6744AB |
| 廠商： | INTERSIL CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | Octal Buffers/Drivers With 3-State Outputs 20-SOIC -40 to 85 |
| 中文描述： | 1 A SWITCHING CONTROLLER, 2000 kHz SWITCHING FREQ-MAX, PDSO8 |
| 封裝： | PLASTIC, MS-012AA, SOIC-8 |
| 文件頁數(shù)： | 11/18頁 |
| 文件大小： | 403K |
| 代理商： | ISL6744AB |
11
FN9147.8
September 22, 2005
MOSFET Selection
The criteria for selection of the primary side half-bridge FETs
and the secondary side synchronous rectifier FETs is largely
based on the current and voltage rating of the device.
However, the FET drain-source capacitance and gate
charge cannot be ignored.
The zero voltage switch (ZVS) transition timing is dependent
on the transformer’s leakage inductance and the
capacitance at the node between the upper FET source and
the lower FET drain. The node capacitance is comprised of
the drain-source capacitance of the FETs and the
transformer parasitic capacitance. The leakage inductance
and capacitance form an LC resonant tank circuit which
determines the duration of the transition. The amount of
energy stored in the LC tank circuit determines the transition
voltage amplitude. If the leakage inductance energy is too
low, ZVS operation is not possible and near or partial ZVS
operation occurs. As the leakage energy increases, the
voltage amplitude increases until it is clamped by the FET
body diode to ground or V
IN
, depending on which FET
conducts. When the leakage energy exceeds the minimum
required for ZVS operation, the voltage is clamped until the
energy is transferred. This behavior increases the time
window for ZVS operation. This behavior is not without
consequences, however. The transition time and the period
of time during which the voltage is clamped reduces the
effective duty cycle.
The gate charge affects the switching speed of the FETs.
Higher gate charge translates into higher drive requirements
and/or slower switching speeds. The energy required to
drive the gates is dissipated as heat.
The maximum input voltage, V
IN
, plus transient voltage,
determines the voltage rating required. With a maximum
input voltage of 53V for this application, and if we allow a
10% adder for transients, a voltage rating of 60V or higher
will suffice.
FIGURE 7C. INT. LAYER 2: 2 TURNS PRIMARY WINDING
FIGURE 7D. INT. LAYER 3: 2 TURNS PRIMARY WINDING
FIGURE 7E. INT. LAYER 4: 1 TURN SECONDARY WINDING
FIGURE 7F. BOTTOM LAYER: 1 TURN SECONDARY AND SR
WINDINGS
FIGURE 7G. PWB DIMENSIONS
0.689
0.807
0.639
0.403
0.169
0.000
1.054
0.774
0.479
0.184
0.000
0.358
ISL6744
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| ISL6744ABZ | Octal Buffers/Drivers With 3-State Outputs 20-SOIC -40 to 85 |
| ISL6744AU | Octal Buffers/Drivers With 3-State Outputs 20-SOIC -40 to 85 |
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