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參數(shù)資料
| 型號： | ISL6740IB |
| 廠商： | INTERSIL CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | Flexible Double Ended Voltage and Current Mode PWM Controllers |
| 中文描述： | 0.5 A SWITCHING CONTROLLER, 2000 kHz SWITCHING FREQ-MAX, PDSO16 |
| 封裝： | PLASTIC, MS-012-AC, SOIC-16 |
| 文件頁數(shù)： | 18/29頁 |
| 文件大?。?/td> | 639K |
| 代理商： | ISL6740IB |
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18
MOSFET Selection
The criteria for selection of the primary side half-bridge FETs
and the secondary side synchronous rectifier FETs is largely
based on the current and voltage rating of the device.
However, the FET drain-source capacitance and gate charge
cannot be ignored.
The zero voltage switch (ZVS) transition timing is dependent
on the transformer’s leakage inductance and the
capacitance at the node between the upper FET source and
the lower FET drain. The node capacitance is comprised of
the drain-source capacitance of the FETs and the
transformer parasitic capacitance. The leakage inductance
and capacitance form an LC resonant tank circuit which
determines the duration of the transition. The amount of
energy stored in the LC tank circuit determines the transition
voltage amplitude. If the leakage inductance energy is too
low, ZVS operation is not possible and near or partial ZVS
operation occurs. As the leakage energy increases, the
voltage amplitude increases until it is clamped by the FET
body diode to ground or V
IN
, depending on which FET
conducts. When the leakage energy exceeds the minimum
required for ZVS operation, the voltage is clamped until the
energy is transferred. This behavior increases the time
window for ZVS operation. This behavior is not without
consequences, however. The transition time and the period
of time during which the voltage is clamped reduces the
effective duty cycle.
The gate charge affects the switching speed of the FETs.
Higher gate charge translates into higher drive requirements
and/or slower switching speeds. The energy required to drive
the gates is dissipated as heat.
The maximum input voltage, V
IN
, plus transient voltage,
determines the voltage rating required. With a maximum
input voltage of 53V for this application, and if we allow a
10% adder for transients, a voltage rating of 60V or higher
will suffice.
The RMS current through the each primary side FET can be
determined from EQ. 17, substituting 5A of primary current
for I
OUT
. The result is 3.5A RMS. Fairchild FDS3672 FETs,
rated at 100V and 7.5A (r
DS(ON)
= 22m
), were selected for
the half-bridge switches.
The synchronous rectifier FETs must withstand
approximately one half of the input voltage assuming no
switching transients are present. This suggests a device
capable of withstanding at least 30V is required. Empirical
testing in the circuit revealed switching transients of 20V
were present across the device indicating a rating of at least
60V is required.
The RMS current rating of 7.07A for each SR FET requires a
low r
DS(ON)
to minimize conduction losses, which is difficult to
find in a 60V device. It was decided to use two devices in
parallel to simplify the thermal design. Two Fairchild FDS5670
devices are used in parallel for a total of four SR FETs. The
FDS5670 is rated at 60V and 10A (r
DS(ON)
= 14m
).
Oscillator Component Selection
The desired operating frequency of 235kHz for the converter
was established in the
Design Criteria
section. The
oscillator frequency operates at twice the frequency of the
converter because two clock cycles are required for a
complete converter period.
During each oscillator cycle the timing capacitor, C
T
, must be
charged and discharged. Determining the required
discharge time to achieve zero voltage switching (ZVS) is the
critical design goal in selecting the timing components. The
discharge time sets the deadtime between the two outputs,
and is the same as ZVS transition time. Once the discharge
time is determined, the remainder of the period becomes the
charge time.
The ZVS transition duration is determined by the
transformer’s primary leakage inductance, L
lk
, by the FET
Coss, by the transformer’s parasitic winding capacitance,
and by any other parasitic elements on the node. The
parameters may be determined by measurement,
calculation, estimate, or by some combination of these
methods.
Device output capacitance, Coss, is non-linear with applied
voltage. To find the equivalent discrete capacitance, Cfet, a
charge model is used. Using a known current source, the
time required to charge the MOSFET drain to the desired
operating voltage is determined and the equivalent
capacitance is calculated.
Once the estimated transition time is determined, it must be
verified directly in the application. The transformer leakage
inductance was measured at 125nH and the combined
capacitance was estimated at 2000pF. Calculations indicate
a transition period of ~ 25ns. Verification of the performance
yielded a value of T
D
closer to 45ns.
The remainder of the switching half-period is the charge
time, T
C
, and can be found from
where F
S
is the converter switching frequency.
Using Fig. 4, the capacitor value appropriate to the desired
oscillator operating frequency of 470kHz can be selected. A
C
T
value of 100pF, 220pF, or 330pF is appropriate for this
frequency. A value of 220pF was selected.
t
zvs
π
L
-------------------------------------------------------------------
2C
C
+
(
)
≈
S
(EQ. 19)
Cfet
-------------------
t
=
F
(EQ. 20)
T
C
S
---------------
T
D
–
2
235
10
3
----------------------------------
45
10
9
–
–
2.08
=
=
=
μ
s
(EQ. 21)
ISL6740, ISL6741
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PDF描述 |
|---|---|
| ISL6740IV | Octal Buffers/Drivers With 3-State Outputs 20-SSOP -40 to 85 |
| ISL6741 | Flexible Double Ended Voltage and Current Mode PWM Controllers(靈活的雙端電壓和電流模式PWM控制器) |
| ISL6845IB | Improved Industry Standard Single Ended Current Mode PWM Controller |
| ISL6845 | Improved Industry Standard Single Ended Current Mode PWM Controller |
| ISL6845IRZ-T | Improved Industry Standard Single-Ended Current Mode PWM Controller |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ISL6740IB-T | 功能描述:IC REG CTRLR PWM VM 16-SOIC RoHS:否 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - DC DC 切換控制器 系列:- 標準包裝:2,500 系列:- PWM 型:電流模式 輸出數(shù):1 頻率 - 最大:500kHz 占空比:100% 電源電壓:8.2 V ~ 30 V 降壓:無 升壓:無 回掃:是 反相:無 倍增器:無 除法器:無 Cuk:無 隔離:是 工作溫度:0°C ~ 70°C 封裝/外殼:8-DIP（0.300"，7.62mm） 包裝:管件 產品目錄頁面:1316 (CN2011-ZH PDF) |
| ISL6740IBZ | 功能描述:電壓模式 PWM 控制器 VOLT PWM MODE CONTRL 16LD NSOIC RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:1 拓撲結構:Buck 輸出電壓:34 V 輸出電流: 開關頻率: 工作電源電壓:4.5 V to 5.5 V 電源電流:600 uA 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝 / 箱體:WSON-8 封裝:Reel |
| ISL6740IBZ-T | 功能描述:IC REG CTRLR PWM VM 16-SOIC RoHS:是 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - DC DC 切換控制器 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- PWM 型:電流模式 輸出數(shù):1 頻率 - 最大:275kHz 占空比:50% 電源電壓:18 V ~ 110 V 降壓:無 升壓:無 回掃:無 反相:無 倍增器:無 除法器:無 Cuk:無 隔離:是 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 包裝:帶卷 (TR) |
| ISL6740IV | 功能描述:IC REG CTRLR PWM VM 16-TSSOP RoHS:否 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - DC DC 切換控制器 系列:- 標準包裝:2,500 系列:- PWM 型:電流模式 輸出數(shù):1 頻率 - 最大:500kHz 占空比:100% 電源電壓:8.2 V ~ 30 V 降壓:無 升壓:無 回掃:是 反相:無 倍增器:無 除法器:無 Cuk:無 隔離:是 工作溫度:0°C ~ 70°C 封裝/外殼:8-DIP（0.300"，7.62mm） 包裝:管件 產品目錄頁面:1316 (CN2011-ZH PDF) |
| ISL6740IV-T | 功能描述:IC REG CTRLR PWM VM 16-TSSOP RoHS:否 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - DC DC 切換控制器 系列:- 標準包裝:2,500 系列:- PWM 型:電流模式 輸出數(shù):1 頻率 - 最大:500kHz 占空比:100% 電源電壓:8.2 V ~ 30 V 降壓:無 升壓:無 回掃:是 反相:無 倍增器:無 除法器:無 Cuk:無 隔離:是 工作溫度:0°C ~ 70°C 封裝/外殼:8-DIP（0.300"，7.62mm） 包裝:管件 產品目錄頁面:1316 (CN2011-ZH PDF) |
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