參數(shù)資料
型號： ISL6613CB
廠商： INTERSIL CORP
元件分類： 功率晶體管
英文描述： Advanced Synchronous Rectified Buck MOSFET Drivers with Protection Features
中文描述： 3 A HALF BRDG BASED MOSFET DRIVER, PDSO8
封裝： PLASTIC, MS-012AA, SOIC-8
文件頁數(shù)： 6/12頁
文件大小： 322K
代理商： ISL6613CB
6
FN9153.5
July 25, 2005
Three-State Upper Gate Falling Threshold
VCC = 12V
2.60
V
Shutdown Holdoff Time
t
TSSHD
-
245
-
ns
UGATE Rise Time
t
RU
V
PVCC
= 12V, 3nF Load, 10% to 90%
-
26
-
ns
LGATE Rise Time
t
RL
t
FU
t
FL
t
PDHU
V
PVCC
= 12V, 3nF Load, 10% to 90%
V
PVCC
= 12V, 3nF Load, 90% to 10%
V
PVCC
= 12V, 3nF Load, 90% to 10%
V
PVCC
= 12V, 3nF Load, Adaptive
-
18
-
ns
UGATE Fall Time
-
18
-
ns
LGATE Fall Time
-
12
-
ns
UGATE Turn-On Propagation Delay (Note 4)
-
10
-
ns
LGATE Turn-On Propagation Delay (Note 4)
t
PDHL
V
PVCC
= 12V, 3nF Load, Adaptive
-
10
-
ns
UGATE Turn-Off Propagation Delay (Note 4)
t
PDLU
V
PVCC
= 12V, 3nF Load
-
10
-
ns
LGATE Turn-Off Propagation Delay (Note 4)
t
PDLL
t
PDTS
V
PVCC
= 12V, 3nF Load
V
PVCC
= 12V, 3nF Load
-
10
-
ns
LG/UG Three-State Propagation Delay (Note 4)
-
10
-
ns
OUTPUT (Note 4)
Upper Drive Source Current
I
U_SOURCE
V
PVCC
= 12V, 3nF Load
-
1.25
-
A
Upper Drive Source Impedance
R
U_SOURCE
150mA Source Current
1.25
2.0
3.0
Upper Drive Sink Current
I
U_SINK
V
PVCC
= 12V, 3nF Load
-
2
-
A
Upper Drive Transition Sink Impedance
R
U_SINK_TR
70ns With Respect To PWM Falling
-
1.3
2.2
Upper Drive DC Sink Impedance
R
U_SINK_DC
150mA Source Current
I
L_SOURCE
V
PVCC
= 12V, 3nF Load
R
L_SOURCE
150mA Source Current
I
L_SINK
V
PVCC
= 12V, 3nF Load
0.9
1.65
3.0
Lower Drive Source Current
-
2
-
A
Lower Drive Source Impedance
0.85
1.25
2.2
Lower Drive Sink Current
-
3
-
A
Lower Drive Sink Impedance
R
L_SINK
150mA Sink Current
0.60
0.80
1.35
OVER TEMPERATURE SHUTDOWN
Thermal Shutdown Setpoint
-
150
-
°C
Thermal Recovery Setpoint
-
108
-
°C
NOTE:
4. Guaranteed by design. Not 100% tested in production.
Electrical Specifications
Recommended Operating Conditions, Unless Otherwise Noted.
(Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Functional Pin Description
PACKAGE PIN #
PIN
SYMBOL
FUNCTION
SOIC
DFN
1
1
UGATE
Upper gate drive output. Connect to gate of high-side power N-Channel MOSFET.
2
2
BOOT
Floating bootstrap supply pin for the upper gate drive. Connect the bootstrap capacitor between this pin and the
PHASE pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See the Internal Bootstrap
Device section under DESCRIPTION for guidance in choosing the capacitor value.
-
3,8
N/C
No Connection.
3
4
PWM
The PWM signal is the control input for the driver. The PWM signal can enter three distinct states during operation,
see the three-state PWM Input section under DESCRIPTION for further details. Connect this pin to the PWM output
of the controller.
4
5
GND
Bias and reference ground. All signals are referenced to this node. It is also the power ground return of the driver.
5
6
LGATE
Lower gate drive output. Connect to gate of the low-side power N-Channel MOSFET.
6
7
VCC
Connect this pin to a +12V bias supply. Place a high quality low ESR ceramic capacitor from this pin to GND.
7
9
PVCC
This pin supplies power to both upper and lower gate drives in ISL6613; only the lower gate drive in ISL6612. Its
operating range is +5V to 12V. Place a high quality low ESR ceramic capacitor from this pin to GND.
8
10
PHASE
Connect this pin to the SOURCE of the upper MOSFET and the DRAIN of the lower MOSFET. This pin provides
a return path for the upper gate drive.
9
11
PAD
Connect this pad to the power ground plane (GND) via thermally enhanced connection.
ISL6612, ISL6613
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