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參數(shù)資料
| 型號： | ISL6612 |
| 廠商： | Intersil Corporation |
| 英文描述： | 7-Bit Bus Interfaces With 3-State Outputs 20-SOIC 0 to 70 |
| 中文描述： | 先進的同步整流降壓MOSFET驅(qū)動器的保護功能 |
| 文件頁數(shù)： | 9/12頁 |
| 文件大?。?/td> | 322K |
| 代理商： | ISL6612 |
9
FN9153.5
July 25, 2005
maximum recommended operating junction temperature of
125°C. The maximum allowable IC power dissipation for the
SO8 package is approximately 800mW at room temperature,
while the power dissipation capacity in the EPSOIC and DFN
packages, with an exposed heat escape pad, is more than
2W and 1.5W, respectively. Both EPSOIC and DFN
packages are more suitable for high frequency applications.
See Layout Considerations paragraph for thermal transfer
improvement suggestions. When designing the driver into an
application, it is recommended that the following calculation
is used to ensure safe operation at the desired frequency for
the selected MOSFETs. The total gate drive power losses
due to the gate charge of MOSFETs and the driver’s internal
circuitry and their corresponding average driver current can
be estimated with EQs. 2 and 3, respectively,
where the gate charge (Q
G1
and Q
G2
) is defined at a
particular gate to source voltage (V
GS1
and V
GS2
) in the
corresponding MOSFET datasheet; I
Q
is the driver’s total
quiescent current with no load at both drive outputs; N
Q1
and N
Q2
are number of upper and lower MOSFETs,
respectively; UVCC and LVCC are the drive voltages for
both upper and lower FETs, respectively. The I
Q*
VCC
product is the quiescent power of the driver without
capacitive load and is typically 116mW at 300kHz.
The total gate drive power losses are dissipated among the
resistive components along the transition path. The drive
resistance dissipates a portion of the total gate drive power
losses, the rest will be dissipated by the external gate
resistors (R
G1
and R
G2
) and the internal gate resistors
(R
GI1
and R
GI2
) of MOSFETs. Figures 3 and 4 show the
typical upper and lower gate drives turn-on transition path.
The power dissipation on the driver can be roughly
estimated as:
Layout Considerations
For heat spreading, place copper underneath the IC whether
it has an exposed pad or not. The copper area can be
extended beyond the bottom area of the IC and/or
connected to buried copper plane(s) with thermal vias. This
combination of vias for vertical heat escape, extended
copper plane, and buried planes for heat spreading allows
the IC to achieve its full thermal potential.
Place each channel power component as close to each
other as possible to reduce PCB copper losses and PCB
parasitics: shortest distance between DRAINs of upper FETs
and SOURCEs of lower FETs; shortest distance between
DRAINs of lower FETs and the power ground. Thus, smaller
amplitudes of positive and negative ringing are on the
switching edges of the PHASE node. However, some space
in between the power components is required for good
airflow. The traces from the drivers to the FETs should be
kept short and wide to reduce the inductance of the traces
and to promote clean drive signals.
P
Qg_TOT
P
Qg_Q1
P
Qg_Q2
I
Q
VCC
+
+
=
(EQ. 2)
P
Qg_Q1
Q
---------------------------------------
UVCC
2
GS1
F
SW
N
Q1
=
P
Qg_Q2
Q
--------------------------------------
LVCC
2
GS2
F
SW
N
Q2
=
I
DR
Q
-----------------------------------------------------
UVCC
GS1
N
Q
----------------------------------------------------
LVCC
GS2
N
+
F
SW
I
Q
+
=
(EQ. 3)
FIGURE 3. TYPICAL UPPER-GATE DRIVE TURN-ON PATH
FIGURE 4. TYPICAL LOWER-GATE DRIVE TURN-ON PATH
P
DR
P
DR_UP
P
DR_LOW
I
Q
VCC
+
+
=
(EQ. 4)
P
DR_UP
R
+
R
HI1
R
EXT1
--------------------------------------
R
+
R
LO1
R
EXT1
---------------------------------------
+
P
2
---------------------
=
P
DR_LOW
R
+
R
HI2
R
EXT2
--------------------------------------
R
+
R
LO2
R
EXT2
---------------------------------------
+
P
2
---------------------
=
R
EXT1
R
G1
R
Q1
-------------
+
=
R
EXT2
R
G2
R
N
Q2
-------------
+
=
Q1
D
S
G
R
GI1
R
G1
BOOT
R
HI1
C
DS
C
GS
C
GD
R
LO1
PHASE
UVCC
LVCC
Q2
D
S
G
R
GI2
R
G2
R
HI2
C
DS
C
GS
C
GD
R
LO2
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