參數(shù)資料
型號: ISL6566A
廠商: Intersil Corporation
英文描述: Three-Phase Buck PWM Controller with Two Integrated MOSFET Drivers and One External Driver Signal
中文描述: 三相降壓PWM控制器,帶有兩個(gè)集成MOSFET驅(qū)動(dòng)器和一個(gè)外部驅(qū)動(dòng)器的信號
文件頁數(shù): 23/28頁
文件大?。?/td> 784K
代理商: ISL6566A
23
FN9200.2
July 27, 2005
per-channel switching frequency. The values of the
compensation components depend on the relationships of f
0
to the L-C pole frequency and the ESR zero frequency. For
each of the following three, there is a separate set of
equations for the compensation components.
In Equations 29, L is the per-channel filter inductance
divided by the number of active channels; C is the sum total
of all output capacitors; ESR is the equivalent series
resistance of the bulk output filter capacitance; and V
PP
is
the peak-to-peak sawtooth signal amplitude as described in
the
Electrical Specifications
.
Once selected, the compensation values in Equations 29
assure a stable converter with reasonable transient
performance. In most cases, transient performance can be
improved by making adjustments to R
C
. Slowly increase the
value of R
C
while observing the transient performance on an
oscilloscope until no further improvement is noted. Normally,
C
C
will not need adjustment. Keep the value of C
C
from
Equations 29 unless some performance issue is noted.
The optional capacitor C
2
, is sometimes needed to bypass
noise away from the PWM comparator (see Figure 20). Keep
a position available for C
2
, and be prepared to install a high-
frequency capacitor of between 22pF and 150pF in case any
leading edge jitter problem is noted.
Output Filter Design
The output inductors and the output capacitor bank together
to form a low-pass filter responsible for smoothing the
pulsating voltage at the phase nodes. The output filter also
must provide the transient energy until the regulator can
respond. Because it has a low bandwidth compared to the
switching frequency, the output filter limits the system
transient response. The output capacitors must supply or
sink load current while the current in the output inductors
increases or decreases to meet the demand.
In high-speed converters, the output capacitor bank is usually
the most costly (and often the largest) part of the circuit.
Output filter design begins with minimizing the cost of this part
of the circuit. The critical load parameters in choosing the
output capacitors are the maximum size of the load step,
I,
the load-current slew rate, di/dt, and the maximum allowable
output-voltage deviation under transient loading,
V
MAX
.
Capacitors are characterized according to their capacitance,
ESR, and ESL (equivalent series inductance).
At the beginning of the load transient, the output capacitors
supply all of the transient current. The output voltage will
initially deviate by an amount approximated by the voltage
drop across the ESL. As the load current increases, the
voltage drop across the ESR increases linearly until the load
current reaches its final value. The capacitors selected must
have sufficiently low ESL and ESR so that the total output-
voltage deviation is less than the allowable maximum.
Neglecting the contribution of inductor current and regulator
response, the output voltage initially deviates by an amount
The filter capacitor must have sufficiently low ESL and ESR
so that
V <
V
MAX
.
Most capacitor solutions rely on a mixture of high frequency
capacitors with relatively low capacitance in combination
with bulk capacitors having high capacitance but limited
high-frequency performance. Minimizing the ESL of the
high-frequency capacitors allows them to support the output
voltage as the current increases. Minimizing the ESR of the
bulk capacitors allows them to supply the increased current
with less output voltage deviation.
The ESR of the bulk capacitors also creates the majority of
the output-voltage ripple. As the bulk capacitors sink and
source the inductor ac ripple current (see
Interleaving
and
Equation 2), a voltage develops across the bulk capacitor
ESR equal to I
C,PP
(ESR). Thus, once the output capacitors
are selected, the maximum allowable ripple voltage,
V
PP(MAX)
, determines the lower limit on the inductance.
Since the capacitors are supplying a decreasing portion of
the load current while the regulator recovers from the
transient, the capacitor voltage becomes slightly depleted.
The output inductors must be capable of assuming the entire
load current before the output voltage decreases more than
V
MAX
. This places an upper limit on inductance.
2
π
LC
-------1
f
0
>
R
C
R
FB
2
π
f
V
LC
IN
0.66V
π
V
PP
R
FB
f
0
-------0.66V
=
C
C
2
=
Case 1:
2
π
LC
--------1
f
0
π
C ESR
)
2
<
R
C
R
FB
V
2
π
0.66 V
IN
0.66V
)
2
f
02
V
PP
R
FB
LC
2
0
2
LC
-----------------------------f
=
C
C
2
π
(
------------------------------------------------------------
=
Case 2:
(EQ. 29)
f
0
π
C ESR
)
2
>
R
C
R
FB
2
π
f
V
L
IN
ESR
(
)
0.66 V
=
C
C
0.66V
ESR
2
π
V
PP
R
FB
f
0
L
-------------------------------------------- C
=
Case 3:
V
ESL
(
)
di
dt
----
ESR
(
)
I
+
(EQ. 30)
L
ESR
(
)
V
IN
--------f
NV
OUT
S
V
IN
V
PP MAX
V
OUT
)
(EQ. 31)
ISL6566A
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